255 lines
8.6 KiB
C
255 lines
8.6 KiB
C
/*
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* Copyright (c) 1988 University of Utah.
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* Copyright (c) 1982, 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1992, 1993 BCDL Labs. All rights reserved.
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* Allen Briggs, Chris Caputo, Michael Finch, Brad Grantham, Lawrence Kesteloot
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* Redistribution of this source code or any part thereof is permitted,
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* provided that the following conditions are met:
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* 1) Utilized source contains the copyright message above, this list
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* of conditions, and the following disclaimer.
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* 2) Binary objects containing compiled source reproduce the
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* copyright notice above on startup.
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*
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* CAVEAT: This source code is provided "as-is" by BCDL Labs, and any
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* warranties of ANY kind are disclaimed. We don't even claim that it
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* won't crash your hard disk. Basically, we want a little credit if
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* it works, but we don't want to get mail-bombed if it doesn't.
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*/
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/*
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* from: Utah $Hdr: cpu.h 1.16 91/03/25$
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*
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* from: @(#)cpu.h 7.7 (Berkeley) 6/27/91
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* $Id: cpu.h,v 1.4 1994/01/17 01:04:08 briggs Exp $
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*/
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/*
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ALICE
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BG -- Sat May 23 23:58:23 EDT 1992
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Exported defines and stuff unique to mac68k.
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A lot of this stuff is really specific to the m68k, not just the macs,
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but there isn't time to do anything about that right now...
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*/
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/*
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* definitions of cpu-dependent requirements
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* referenced in generic code
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*/
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#define COPY_SIGCODE /* copy sigcode above user stack in exec */
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/*
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* function vs. inline configuration;
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* these are defined to get generic functions
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* rather than inline or machine-dependent implementations
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*/
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#define NEED_MINMAX /* need {,i,l,ul}{min,max} functions */
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#undef NEED_FFS /* don't need ffs function */
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#undef NEED_BCMP /* don't need bcmp function */
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#undef NEED_STRLEN /* don't need strlen function */
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/* ALICE BG -- Sun May 24 11:31:35 EDT 1992 -- what the hell do these things */
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/* do? */
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#define cpu_exec(p) /* nothing */
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#define cpu_wait(p) /* nothing */
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/*
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* Arguments to hardclock, softclock and gatherstats
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* encapsulate the previous machine state in an opaque
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* clockframe; for hp300, use just what the hardware
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* leaves on the stack.
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*/
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/* ALICE 05/23/92 BG -- Oh, no. What does a VIA intleave on the stack? */
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/* ALICE 06/27/92 LK -- Make sure hardware clock routine does this: */
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typedef struct intrframe {
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int pc;
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int ps;
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} clockframe;
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#define CLKF_USERMODE(framep) (((framep)->ps & PSL_S) == 0)
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#define CLKF_BASEPRI(framep) (((framep)->ps & PSL_IPL7) == 0)
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#define CLKF_PC(framep) ((framep)->pc)
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/*
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* Preempt the current process if in interrupt from user mode,
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* or after the current trap/syscall if in system mode.
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*/
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#define need_resched() { want_resched++; aston(); }
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/*
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* Give a profiling tick to the current process from the softclock
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* interrupt. Request an ast to send us through trap(),
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* marking the proc as needing a profiling tick.
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*/
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#define profile_tick(p, framep) { (p)->p_flag |= SOWEUPC; aston(); }
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/*
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* Notify the current process (p) that it has a signal pending,
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* process as soon as possible.
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*/
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#define signotify(p) aston()
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#define aston() (astpending++)
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int astpending; /* need to trap before returning to user mode */
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int want_resched; /* resched() was called */
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/*
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* simulated software interrupt register
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*/
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extern unsigned char ssir;
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#define SIR_NET 0x1
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#define SIR_CLOCK 0x2
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#define SIR_SERIAL 0x4
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#define siroff(x) ssir &= ~(x)
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#define setsoftnet() ssir |= SIR_NET
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#define setsoftclock() ssir |= SIR_CLOCK
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#define setsoftserial() ssir |= SIR_SERIAL
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/* values for machineid */
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/* BARF MF - some values from the thinkc gesalt include file */
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#define MACH_MAC2 6
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#define MACH_MAC2X 7
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#define MACH_MAC2SI 18
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#define MACH_MAC2CI 11
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#define MACH_MAC2CX 8
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#define MACH_MACSE30 9
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#define MACH_MAC2FX 13
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/* MF processor passed in */
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#define MACH_68020 0
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#define MACH_68030 1
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#define MACH_68040 2
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#define MACH_PENTIUM 3 /* 66 and 99 MHz versions *only* */
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/* values for cpuspeed (not really related to clock speed due to caches) */
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#define MHZ_8 1
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#define MHZ_16 2
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#define MHZ_25 3
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#define MHZ_33 4
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#define MHZ_40 5
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#ifdef KERNEL
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extern int machineid, ectype;
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extern char *intiobase, *intiolimit;
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extern char *extiobase, *extiolimit;
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#endif
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/* physical memory sections */
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#define ROMBASE (0x40000000)
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#define INTIOBASE (0x50000000)
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#define INTIOTOP (0x51000000) /* ~ 128 K */
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#define IIOMAPSIZE btoc(INTIOTOP - INTIOBASE)
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/* ALICE 05/23/92 BG -- These need to be changed. */
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#ifdef NO_SUPER_SPACE_YET
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#define NBSBASE 0x60000000 /* NUBUS Super space */
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#define NBSTOP 0xF0000000
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#endif
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#define NBBASE 0xF9000000 /* NUBUS space */
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#define NBTOP 0xFF000000 /* NUBUS space */
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#define NBMAPSIZE btoc(NBTOP-NBBASE) /* ~ 96 megs */
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#define NBMEMSIZE 0x01000000 /* 16 megs per card */
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#define NBROMOFFSET 0x00FF0000 /* Last 64K == ROM */
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/*
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* IO space:
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*
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* Internal IO space is mapped in the kernel from ``intiobase'' to
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* ``intiolimit'' (defined in locore.s). Since it is always mapped,
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* conversion between physical and kernel virtual addresses is easy.
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*/
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#define ISIIOVA(va) \
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((char *)(va) >= intiobase && (char *)(va) < intiolimit)
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#define IIOV(pa) ((int)(pa)-INTIOBASE+(int)intiobase)
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#define IIOP(va) ((int)(va)-(int)intiobase+INTIOBASE)
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#define IIOPOFF(pa) ((int)(pa)-INTIOBASE)
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/*
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ALICE 05/24/92,13:25:19 BG -- We need to make sure to map NuBus memory in
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the kernel, too.
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ALICE 06/29/92,20:40:00 LK -- I did that, thank you very much. Been there.
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*/
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/*
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* 68851 and 68030 MMU
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*/
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#define PMMU_LVLMASK 0x0007
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#define PMMU_INV 0x0400
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#define PMMU_WP 0x0800
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#define PMMU_ALV 0x1000
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#define PMMU_SO 0x2000
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#define PMMU_LV 0x4000
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#define PMMU_BE 0x8000
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#define PMMU_FAULT (PMMU_WP|PMMU_INV)
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/* 680X0 function codes */
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#define FC_USERD 1 /* user data space */
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#define FC_USERP 2 /* user program space */
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#define FC_SUPERD 5 /* supervisor data space */
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#define FC_SUPERP 6 /* supervisor program space */
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#define FC_CPU 7 /* CPU space */
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/* fields in the 68020 cache control register */
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#define IC_ENABLE 0x0001 /* enable instruction cache */
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#define IC_FREEZE 0x0002 /* freeze instruction cache */
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#define IC_CE 0x0004 /* clear instruction cache entry */
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#define IC_CLR 0x0008 /* clear entire instruction cache */
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/* additional fields in the 68030 cache control register */
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#define IC_BE 0x0010 /* instruction burst enable */
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#define DC_ENABLE 0x0100 /* data cache enable */
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#define DC_FREEZE 0x0200 /* data cache freeze */
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#define DC_CE 0x0400 /* clear data cache entry */
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#define DC_CLR 0x0800 /* clear entire data cache */
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#define DC_BE 0x1000 /* data burst enable */
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#define DC_WA 0x2000 /* write allocate */
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#define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
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#define CACHE_OFF (DC_CLR|IC_CLR)
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#define CACHE_CLR (CACHE_ON)
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#define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
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#define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE)
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