259 lines
8.0 KiB
C
259 lines
8.0 KiB
C
/* $NetBSD: ixdp425_pci.c,v 1.4 2003/10/11 03:53:52 ichiro Exp $ */
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#define PCI_DEBUG
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/*
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* Copyright (c) 2003
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* Ichiro FUKUHARA <ichiro@ichiro.org>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Ichiro FUKUHARA.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ixdp425_pci.c,v 1.4 2003/10/11 03:53:52 ichiro Exp $");
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/*
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* IXDP425 PCI interrupt support.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <machine/autoconf.h>
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#include <machine/bus.h>
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#include <evbarm/ixdp425/ixdp425reg.h>
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#include <evbarm/ixdp425/ixdp425var.h>
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#include <arm/xscale/ixp425reg.h>
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#include <arm/xscale/ixp425var.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/ppbreg.h>
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static int ixdp425_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
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static const char *ixdp425_pci_intr_string(void *, pci_intr_handle_t);
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static const struct evcnt *ixdp425_pci_intr_evcnt(void *, pci_intr_handle_t);
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static void *ixdp425_pci_intr_establish(void *, pci_intr_handle_t, int,
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int (*func)(void *), void *);
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static void ixdp425_pci_intr_disestablish(void *, void *);
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void
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ixp425_md_pci_init(struct ixp425_softc *sc)
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{
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pci_chipset_tag_t pc = &sc->ia_pci_chipset;
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u_int32_t reg;
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/*
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* PCI initialization
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*/
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pc->pc_intr_v = sc;
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pc->pc_intr_map = ixdp425_pci_intr_map;
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pc->pc_intr_string = ixdp425_pci_intr_string;
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pc->pc_intr_evcnt = ixdp425_pci_intr_evcnt;
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pc->pc_intr_establish = ixdp425_pci_intr_establish;
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pc->pc_intr_disestablish = ixdp425_pci_intr_disestablish;
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/* PCI Reset Assert */
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reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);
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GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg & ~(1U << GPIO_PCI_RESET));
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/* PCI Clock Disable */
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reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);
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GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg & ~GPCLKR_MUX14);
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/*
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* set GPIO Direction
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* Output: PCI_CLK, PCI_RESET
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* Input: PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD
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*/
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reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOER);
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reg &= ~(1U << GPIO_PCI_CLK);
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reg &= ~(1U << GPIO_PCI_RESET);
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reg |= ((1U << GPIO_PCI_INTA) | (1U << GPIO_PCI_INTB) |
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(1U << GPIO_PCI_INTC) | (1U << GPIO_PCI_INTD));
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GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOER, reg);
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/* clear ISR */
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GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPISR,
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(1U << GPIO_PCI_INTA) | (1U << GPIO_PCI_INTB) |
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(1U << GPIO_PCI_INTC) | (1U << GPIO_PCI_INTD));
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/* wait 1ms to satisfy "minimum reset assertion time" of the PCI spec */
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DELAY(1000);
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reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);
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GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg |
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(0xf << GPCLKR_CLK0DC_SHIFT) | (0xf << GPCLKR_CLK0TC_SHIFT));
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/* PCI Clock Enable */
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reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);
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GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg | GPCLKR_MUX14);
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/*
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* wait 100us to satisfy "minimum reset assertion time from clock stable
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* requirement of the PCI spec
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*/
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DELAY(100);
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/* PCI Reset deassert */
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reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);
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GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg | (1U << GPIO_PCI_RESET));
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/*
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* AHB->PCI address translation
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* PCI Memory Map allocation in 0x48000000 (64MB)
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* see. IXP425_PCI_MEM_HWBASE
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*/
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PCI_CSR_WRITE_4(sc, PCI_PCIMEMBASE, 0x48494a4b);
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/*
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* PCI->AHB address translation
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* begin at the physical memory start + OFFSET
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*/
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#define AHB_OFFSET 0x10000000UL
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PCI_CSR_WRITE_4(sc, PCI_AHBMEMBASE,
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(AHB_OFFSET & 0xFF000000) +
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((AHB_OFFSET & 0xFF000000) >> 8) +
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((AHB_OFFSET & 0xFF000000) >> 16) +
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((AHB_OFFSET & 0xFF000000) >> 24) +
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0x00010203);
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/* write Mapping registers PCI Configuration Registers */
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/* Base Address 0 - 3 */
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ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR0, AHB_OFFSET + 0x00000000);
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ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR1, AHB_OFFSET + 0x01000000);
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ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR2, AHB_OFFSET + 0x02000000);
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ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR3, AHB_OFFSET + 0x03000000);
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/* Base Address 4 */
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ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR4, 0xffffffff);
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/* Base Address 5 */
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ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR5, 0x00000000);
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/* assert some PCI errors */
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PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_AHBE | ISR_PPE | ISR_PFE | ISR_PSE);
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/*
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* Set up byte lane swapping between little-endian PCI
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* and the big-endian AHB bus
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*/
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PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE | CSR_PDS);
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/*
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* Enable bus mastering and I/O,memory access
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*/
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ixp425_pci_conf_reg_write(sc, PCI_COMMAND_STATUS_REG,
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PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
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PCI_COMMAND_MASTER_ENABLE);
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}
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void
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ixp425_md_pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int pin,
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int swiz, int *ilinep)
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{
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if (bus == 0)
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*ilinep = ((swiz + (dev + pin - 1)) & 3);
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else
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panic("ixp425_md_pci_conf_interrupt: unsupported bus number");
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}
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#define IXP425_MAX_DEV 4
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#define IXP425_MAX_LINE 4
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static int
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ixdp425_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
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{
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static int ixp425_pci_table[IXP425_MAX_DEV][IXP425_MAX_LINE] =
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{
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{PCI_INT_A, PCI_INT_B, PCI_INT_C, PCI_INT_D},
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{PCI_INT_B, PCI_INT_C, PCI_INT_D, PCI_INT_A},
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{PCI_INT_C, PCI_INT_D, PCI_INT_A, PCI_INT_B},
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{PCI_INT_D, PCI_INT_A, PCI_INT_B, PCI_INT_C},
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};
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int pin = pa->pa_intrpin;
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int dev = pa->pa_device;
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#ifdef PCI_DEBUG
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void *v = pa->pa_pc;
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int line = pa->pa_intrline;
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pcitag_t intrtag = pa->pa_intrtag;
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printf("ixdp425_pci_intr_map: v=%p, tag=%08lx intrpin=%d line=%d dev=%d\n",
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v, intrtag, pin, line, dev);
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#endif
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if (pin >= 1 && pin <= IXP425_MAX_LINE &&
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dev >= 1 && dev <= IXP425_MAX_DEV) {
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*ihp = ixp425_pci_table[dev - 1][pin - 1];
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return (0);
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} else {
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printf("ixdp425_pci_intr_map: no mapping for %d/%d/%d\n",
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pa->pa_bus, pa->pa_device, pa->pa_function);
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return (1);
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}
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}
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static const char *
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ixdp425_pci_intr_string(void *v, pci_intr_handle_t ih)
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{
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static char irqstr[IRQNAMESIZE];
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sprintf(irqstr, "ixp425 irq %ld", ih);
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return (irqstr);
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}
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static const struct evcnt *
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ixdp425_pci_intr_evcnt(void *v, pci_intr_handle_t ih)
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{
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return (NULL);
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}
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static void *
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ixdp425_pci_intr_establish(void *v, pci_intr_handle_t ih, int ipl,
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int (*func)(void *), void *arg)
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{
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#ifdef PCI_DEBUG
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printf("ixdp425_pci_intr_establish(v=%p, irq=%d, ipl=%d, func=%p, arg=%p)\n",
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v, (int) ih, ipl, func, arg);
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#endif
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return (ixp425_intr_establish(ih, ipl, func, arg));
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}
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static void
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ixdp425_pci_intr_disestablish(void *v, void *cookie)
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{
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#ifdef PCI_DEBUG
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printf("ixdp425_pci_intr_disestablish(v=%p, cookie=%p)\n",
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v, cookie);
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#endif
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ixp425_intr_disestablish(cookie);
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}
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