89 lines
3.7 KiB
C
89 lines
3.7 KiB
C
/* $NetBSD: sfbreg.h,v 1.2 1999/10/20 02:44:48 nisimura Exp $ */
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/*
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* Copyright (c) 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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/*
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* Smart ("CXTurbo") Frame Buffer definitions, from:
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* ``DEC 3000 300/400/500/600/700/800/900 AXP Models System Prgrammer's Manual''
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* (DEC order number EK-D3SYS-PM), section 6.
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*
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* All definitions are in "dense" TURBOchannel space.
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*/
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/*
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* Size of the SFB address space.
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*/
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#define SFB_SIZE 0x1000000
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/*
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* Offsets into slot space of each functional unit.
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*/
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#define SFB_ASIC_OFFSET 0x0100000 /* SFB ASIC Control Registers */
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#define SFB_ASIC_SIZE 0x0020000
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#define SFB_RAMDAC_OFFSET 0x01c0000 /* BrookTree RAMDAC */
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#define SFB_RAMDAC_SIZE 0x0040000
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#define SFB_FB_OFFSET 0x0200000 /* Frame buffer */
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#define SFB_FB_SIZE 0x0200000
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#define SFB_OSBM_OFFSET 0x0600000 /* Off-screen buffer memory */
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#define SFB_OSBM_SIZE 0x0200000
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/*
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* SFB ASIC registers (offsets from SFB_ASIC_OFFSET).
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*/
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#define SFB_ASIC_COPYBUF_0 0x0000 /* Copy buffer register 0 (R/W) */
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#define SFB_ASIC_COPYBUF_1 0x0004 /* Copy buffer register 1 (R/W) */
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#define SFB_ASIC_COPYBUF_2 0x0008 /* Copy buffer register 2 (R/W) */
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#define SFB_ASIC_COPYBUF_3 0x000c /* Copy buffer register 3 (R/W) */
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#define SFB_ASIC_COPYBUF_4 0x0010 /* Copy buffer register 4 (R/W) */
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#define SFB_ASIC_COPYBUF_5 0x0014 /* Copy buffer register 5 (R/W) */
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#define SFB_ASIC_COPYBUF_6 0x0018 /* Copy buffer register 6 (R/W) */
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#define SFB_ASIC_COPYBUF_7 0x001c /* Copy buffer register 7 (R/W) */
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#define SFB_ASIC_FG 0x0020 /* Foreground (R/W) */
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#define SFB_ASIC_BG 0x0024 /* Background (R/W) */
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#define SFB_ASIC_PLANEMASK 0x0028 /* PlaneMask (R/W) */
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#define SFB_ASIC_PIXELMASK 0x002c /* PixelMask (R/W) */
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#define SFB_ASIC_MODE 0x0030 /* Mode (R/W) */
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#define SFB_ASIC_ROP 0x0034 /* RasterOp (R/W) */
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#define SFB_ASIC_PIXELSHIFT 0x0038 /* PixelShift (R/W) */
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#define SFB_ASIC_ADDRESS 0x003c /* Address (R/W) */
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#define SFB_ASIC_BRES1 0x0040 /* Bresenham register 1 (R/W) */
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#define SFB_ASIC_BRES2 0x0044 /* Bresenham register 2 (R/W) */
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#define SFB_ASIC_BRES3 0x0048 /* Bresenham register 3 (R/W) */
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#define SFB_ASIC_BCONT 0x004c /* Bcont (W) */
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#define SFB_ASIC_DEEP 0x0050 /* Deep (R/W) */
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#define SFB_ASIC_START 0x0054 /* Start (W) */
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#define SFB_ASIC_CLEAR_INTR 0x0058 /* Clear Interrupt (W) */
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#define SFB_ASIC_VIDEO_REFRESH 0x0060 /* Video refresh counter (R/W) */
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#define SFB_ASIC_VIDEO_HSETUP 0x0064 /* Video horizontal setup (R/W) */
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#define SFB_ASIC_VIDEO_VSETUP 0x0068 /* Video vertical setup (R/W) */
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#define SFB_ASIC_VIDEO_BASE 0x006c /* Video base address (R/W) */
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#define SFB_ASIC_VIDEO_VALID 0x0070 /* Video valid (W) */
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#define SFB_ASIC_ENABLE_INTR 0x0074 /* Enable/Disable Interrupts (W) */
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#define SFB_ASIC_TCCLK 0x0078 /* TCCLK count (R/W) */
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#define SFB_ASIC_VIDCLK 0x007c /* VIDCLK count (R/W) */
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