pk cd955b850f Bits 0 (MMU Enable) and 1 (Fault inhibit) are common among the implementations ... of the SRMMU control register. Reflect that fact in the definitions here. Also add the swift `store allocate' bit.		2004-04-27 13:05:38 +00:00
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compile
conf	Default to not inlining __cpu_simple_lock().	2004-04-20 15:55:30 +00:00
dev	Update for new pci_devinfo(9) signature.	2004-04-24 15:49:00 +00:00
fpu	Simplify fpu_cleanup() by having it return a code to indicate that a SIGFPE	2003-10-12 19:48:52 +00:00
include	Bits 0 (MMU Enable) and 1 (Fault inhibit) are common among the implementations	2004-04-27 13:05:38 +00:00
sparc	Add instrumentation for `PMEG' management on sun4/4c.	2004-04-27 11:26:43 +00:00
stand	compat mode: skip double map at VA 0 if the physical load address is 0.	2004-04-08 07:35:34 +00:00
Makefile