195 lines
5.7 KiB
C
195 lines
5.7 KiB
C
/* $NetBSD: intcreg.h,v 1.1 2002/07/05 13:31:53 scw Exp $ */
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/*
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* Copyright 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Steve C. Woodford for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SH5_INTCREG_H
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#define _SH5_INTCREG_H
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/*
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* Interrupt Control Register: SET
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*
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* 1 <= (n) <= 15
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*/
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#define INTC_REG_ICR_SET 0x00
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#define INTC_ICR_SET_IRL_MODE_INDEP 1
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#define INTC_ICR_SET_ICRn(n) (2 << (n))
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/*
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* Interrupt Control Register: CLEAR
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*
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* 1 <= (n) <= 15
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*/
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#define INTC_REG_ICR_CLEAR 0x08
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#define INTC_ICR_CLEAR_IRL_MODE_LEVEL 1
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#define INTC_ICR_CLEAR_ICRn(n) (2 << (n))
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/*
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* Interrupt Priorities Register
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*
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* 0 <= (n) <= 63
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*/
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#define INTC_REG_INTPRI(n) (0x10 + ((n) & 0x38))
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#define INTC_INTPRI_MASK 0x0f
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#define INTC_INTPRI_SHIFT(n) (((n) & 0x7) * 4)
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/*
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* Interrupt Enable Registers
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*
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* 0 <= (n) <= 63
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*/
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#define INTC_REG_INTENB(n) (0x70 + (8 * ((n) / 32)))
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#define INTC_INTENB_BIT(n) (1 << ((n) & 0x1f))
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#define INTC_INTENB_ALL 0xffffffffu
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/*
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* Interrupt Disable Registers
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*
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* 0 <= (n) <= 63
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*/
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#define INTC_REG_INTDISB(n) (0x80 + (8 * ((n) / 32)))
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#define INTC_INTDISB_BIT(n) (1 << ((n) & 0x1f))
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#define INTC_INTDISB_ALL 0xffffffffu
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/*
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* Interrupt Source Status Registers
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*
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* 0 <= (n) <= 63
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*/
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#define INTC_REG_INTSRC(n) (0x50 + (8 * ((n) / 32)))
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#define INTC_INTSRC_BIT(n) (1 << ((n) & 0x1f))
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/*
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* Interrupt Request Status Registers
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*
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* 0 <= (n) <= 63
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*/
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#define INTC_REG_INTREQ(n) (0x60 + (8 * ((n) / 32)))
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#define INTC_INTREQ_BIT(n) (1 << ((n) & 0x1f))
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/* Size of INTC register area */
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#define INTC_REG_SIZE 0x90
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/* How many interrupts */
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#define INTC_N_IRQS 64
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/*
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* Given a priority, evaluate the corresponding INTEVT value for
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* level encoded "IRL" pin interrupts.
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*/
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#define INTC_IRL_PRI2INTEVT(p) (0x200 + ((15 - (p)) * 0x20))
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/*
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* The opposite of the above macro...
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*/
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#define INTC_IRL_INTEVT2PRI(e) (15 - (((e) - 0x200) / 0x20))
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/*
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* Non-level encoded IRL INTEVT/INUM values
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*/
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#define INTC_INTEVT_IRL0 0x240
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#define INTC_INUM_IRL0 0
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#define INTC_INTEVT_IRL1 0x2a0
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#define INTC_INUM_IRL1 1
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#define INTC_INTEVT_IRL2 0x300
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#define INTC_INUM_IRL2 2
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#define INTC_INTEVT_IRL3 0x360
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#define INTC_INUM_IRL3 3
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/*
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* INTEVT/INUM values for on-chip resources
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*/
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#define INTC_INTEVT_PCI_INTA 0x800
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#define INTC_INUM_PCI_INTA 4
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#define INTC_INTEVT_PCI_INTB 0x820
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#define INTC_INUM_PCI_INTB 5
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#define INTC_INTEVT_PCI_INTC 0x840
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#define INTC_INUM_PCI_INTC 6
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#define INTC_INTEVT_PCI_INTD 0x860
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#define INTC_INUM_PCI_INTD 7
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#define INTC_INTEVT_PCI_SERR 0xa00
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#define INTC_INUM_PCI_SERR 12
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#define INTC_INTEVT_PCI_ERR 0xa20
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#define INTC_INUM_PCI_ERR 13
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#define INTC_INTEVT_PCI_PWR3 0xa40
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#define INTC_INUM_PCI_PWR3 14
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#define INTC_INTEVT_PCI_PWR2 0xa60
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#define INTC_INUM_PCI_PWR2 15
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#define INTC_INTEVT_PCI_PWR1 0xa80
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#define INTC_INUM_PCI_PWR1 16
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#define INTC_INTEVT_PCI_PWR0 0xaa0
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#define INTC_INUM_PCI_PWR0 17
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#define INTC_INTEVT_DMAC_DMTE0 0x640
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#define INTC_INUM_DMAC_DMTE0 18
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#define INTC_INTEVT_DMAC_DMTE1 0x660
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#define INTC_INUM_DMAC_DMTE1 19
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#define INTC_INTEVT_DMAC_DMTE2 0x680
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#define INTC_INUM_DMAC_DMTE2 20
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#define INTC_INTEVT_DMAC_DMTE3 0x6a0
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#define INTC_INUM_DMAC_DMTE3 21
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#define INTC_INTEVT_DMAC_DAERR 0x6c0
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#define INTC_INUM_DMAC_DAERR 22
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#define INTC_INTEVT_TMU_TUNI0 0x400
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#define INTC_INUM_TMU_TUNI0 32
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#define INTC_INTEVT_TMU_TUNI1 0x420
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#define INTC_INUM_TMU_TUNI1 33
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#define INTC_INTEVT_TMU_TUNI2 0x440
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#define INTC_INUM_TMU_TUNI2 34
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#define INTC_INTEVT_TMU_TICPI2 0x460
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#define INTC_INUM_TMU_TICPI2 35
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#define INTC_INTEVT_RTC_ATI 0x480
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#define INTC_INUM_RTC_ATI 36
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#define INTC_INTEVT_RTC_PRI 0x4a0
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#define INTC_INUM_RTC_PRI 37
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#define INTC_INTEVT_RTC_CUI 0x4c0
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#define INTC_INUM_RTC_CUI 38
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#define INTC_INTEVT_SCIF_ERI 0x700
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#define INTC_INUM_SCIF_ERI 39
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#define INTC_INTEVT_SCIF_RXI 0x720
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#define INTC_INUM_SCIF_RXI 40
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#define INTC_INTEVT_SCIF_BRI 0x740
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#define INTC_INUM_SCIF_BRI 41
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#define INTC_INTEVT_SCIF_TXI 0x760
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#define INTC_INUM_SCIF_TXI 42
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#define INTC_INTEVT_WDT_ITI 0x560
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#define INTC_INUM_WDT_ITI 63
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#endif /* _SH5_INTCREG_H */
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