123 lines
4.5 KiB
C
123 lines
4.5 KiB
C
/* $NetBSD: rambo.h,v 1.5 2006/09/15 16:37:19 gdamore Exp $ */
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/*-
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Wayne Knowles
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* RAMBO DMA controller/timer asic used on the Mips 3230 (Pizazz)
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*/
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#ifndef _MACHINE_RAMBO_H
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#define _MACHINE_RAMBO_H 1
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/* Register laytout of a single RAMBO DMA channel */
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struct rambo_ch {
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u_long dma_laddr; /* DMA load address reg 32b R/W */
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u_long __0[63];
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u_long dma_diag; /* DMA Diagnostic reg 32b R */
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u_long __1[63];
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u_short __2;
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u_short dma_fifo; /* FIFO Buffer 16 bits 16b R/W */
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u_long __3[63];
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u_long dma_mode; /* DMA Mode Register 32b R/W */
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u_long __4[63];
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u_short __5;
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u_short dma_block; /* DMA Block Count 16b R/W */
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u_long __6[63];
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u_long dma_caddr; /* DMA Current Address 32b R */
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u_long __7[63];
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};
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#define RAMBO_LADDR 0x0000
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#define RAMBO_DIAG 0x0100
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#define RAMBO_FIFO 0x0202
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#define RAMBO_MODE 0x0300
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#define RAMBO_BLKCNT 0x0402
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#define RAMBO_CADDR 0x0500
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/* DMA mode register (dma_mode) (R/W) */
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#define RB_CLRFIFO 0x80000000 /* Clear DMA FIFO */
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#define RB_DMA_ENABLE 0x40000000 /* Enable DMA Transfer */
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#define RB_AUTORELOAD 0x20000000 /* Auto restart DMA */
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#define RB_INT_ENABLE 0X10000000 /* INterrupt on terminal count */
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#define RB_DMA_WR 0x08000000 /* Xfer into memory */
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#define RB_DMA_RD 0x00000000 /* Xfer from memory */
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#define RB_CLRERROR 0x04000000 /* Clear DMA Error register */
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/* status bits of mode register (R) */
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#define RB_FIFO_FULL 0x00000800 /* FIFO Buffer is full */
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#define RB_FIFO_EMPTY 0x00000400 /* FIFO Buffer is empty */
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#define RB_DMA_ERROR 0x00000200 /* Error has occurred */
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#define RB_INTR_PEND 0x00000100 /* Interrupt is pending */
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#define RB_CNT_MASK 0x000000ff /* half-words left in FIFO */
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/* Offsets to other registers in the RAMBO asic */
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#define RB_TCOUNT 0x0c00
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#define RB_TBREAK 0x0d00
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#define RB_ERRREG 0x0e00
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#define RB_CTLREG 0x0f00
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/* Hardware Register */
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#define RB_BUZZ0 0x00 /* 1524 Hz */
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#define RB_BUZZ1 0x10 /* 762 Hz */
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#define RB_BUZZ2 0x20 /* 381 Hz */
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#define RB_BUZZ3 0x30 /* 190 Hz */
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#define RB_BUZZOFF 0x08 /* Buzzer Enable - Active Low */
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#define RB_PARITY_EN 0x04 /* Enable Parity - Active High */
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#define RB_CLR_PAR 0x02 /* Clear SysParErr - Active High */
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#define RB_CLR_IOERR 0x01 /* Clear ErrIntB - Active Low */
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#define RB_BLK_SHIFT 6
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#define RB_BLK_CNT 32 /* half-word byte count */
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#define RB_BLK_MASK 0x3f /* Alignment mask */
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#define RB_BLK_SIZE 64 /* Bytes in a DMA Block */
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/* DMA cannot cross 512k boundry (2^19 == 512k) */
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#define RB_BSIZE 19
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#define RB_BMASK ((1<<RB_BSIZE)-1)
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#define RB_BOUNDRY (1<<RB_BSIZE)
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/* Rambo cycle counter is fed by 25MHz clock then divided by 4 */
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#define RB_FREQUENCY 625000L
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#define HZ_TO_TICKS(hz) (RB_FREQUENCY/(hz))
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#define TICKS_TO_USECS(t) (((t)*4)/25)
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#endif
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