210 lines
7.8 KiB
C
210 lines
7.8 KiB
C
/*
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* Copyright (c) 2006 Itronix Inc.
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* All rights reserved.
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*
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* Ported from Tadpole Solaris sources by Garrett D'Amore for Itronix Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of Itronix Inc. may not be used to endorse
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* or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 2002 by Tadpole Technology
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*/
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#ifndef PSM_H
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#define PSM_H
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#define PSM_PRDL 0x00 /* Posted read data low byte */
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#define PSM_PRDU 0x01 /* Posted read data high byte */
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#define PSM_ISR 0x02 /* Interrupt status register */
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#define PSM_STAT 0x03 /* Status register */
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#define PSM_PSR0 0x04 /* Programmable status register #0 */
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#define PSM_PSR1 0x05 /* Programmable status register #1 */
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#define PSM_PSR2 0x06 /* Programmable status register #2 */
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#define PSM_PSR3 0x07 /* Programmable status register #3 */
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#define PSM_PWDL 0x00 /* Posted write data low byte */
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#define PSM_PWDU 0x01 /* Posted write data high byte */
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#define PSM_IAR 0x02 /* Indirect access register */
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#define PSM_CMR 0x03 /* Command mode register */
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#define PSM_RSV1 0x04 /* Reserved */
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#define PSM_ICR 0x05 /* Interrupt clear register */
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#define PSM_RSV2 0x06 /* Reserved */
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#define PSM_MCR 0x07 /* Master command register */
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/* Interrupt status register defenitions */
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#define PSM_ISR_PO 0x01 /* Power switch activated */
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#define PSM_ISR_DK 0x02 /* System has been docked */
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#define PSM_ISR_UDK 0x04 /* System has been un-docked */
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#define PSM_ISR_LIDO 0x08 /* Transition to clamshell closed */
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#define PSM_ISR_LIDC 0x10 /* Transition to clamshell open */
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#define PSM_ISR_TMP 0x20 /* Over temperature condition detected */
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#define PSM_ISR_BCC 0x40 /* Battery configuration changed */
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#define PSM_ISR_RPD 0x80 /* Request to power down */
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/* Status registert defenitions */
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#define PSM_STAT_AC 0x01 /* Operating under AC power */
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#define PSM_STAT_OVT 0x02 /* Over temperature condition */
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#define PSM_STAT_UN1 0x04 /* Unused */
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#define PSM_STAT_UN2 0x08 /* Unused */
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#define PSM_STAT_ERR 0x10 /* Hardware error occured */
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#define PSM_STAT_MCR 0x20 /* Master Command Register busy */
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#define PSM_STAT_WBF 0x40 /* Write buffer full */
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#define PSM_STAT_RDA 0x80 /* Read data available */
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/* Command Mode Register defenitions */
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#define PSM_CMR_DATA(m,l,d,ra) (ra & 0x07) | \
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((d & 0x01) << 3) | \
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((l & 0x01) << 4) | \
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((m & 0x07) << 5)
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#define PSM_MODE_SYSCFG 0x00 /* System configuration mode */
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#define PSM_MODE_BQRW 0x01 /* Read write battery fuel guage */
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#define PSM_MODE_BCB 0x02 /* Battery status block control */
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#define PSM_MODE_PMPS 0x03 /* Power management policies/status */
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#define PSM_MODE_MISC 0x04 /* Misc. control / status registers */
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#define PSM_MODE_I2C 0x05 /* Direct I2C control */
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#define PSM_MODE_UN1 0x06 /* Unused */
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#define PSM_MODE_UN2 0x07 /* Unused */
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#define PSM_L_8 0x00
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#define PSM_L_16 0x01
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#define PSM_D_WR 0x00
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#define PSM_D_RD 0x01
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/* Master Command Register defenitions */
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#define PSM_MCR_NA1 0x01 /* Not available */
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#define PSM_MCR_NA2 0x02 /* Not available */
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#define PSM_MCR_NA3 0x04 /* Not available */
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#define PSM_MCR_AUTO 0x08 /* Enable active battery management */
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#define PSM_MCR_SD 0x10 /* Shutdown permission granted */
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#define PSM_MCR_MON 0x20 /* Monitor motherboard interrupts/dma */
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#define PSM_MCR_OBP 0x40 /* OBP done notification */
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#define PSM_MCR_RST 0x80 /* Reset PSMbus interface */
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/* Mode dependant registers */
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/* Mode 0 - System configuration */
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#define PSM_SYSCFG_PSSR0 0x00
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#define PSM_SYSCFG_PSCR0 0x01
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#define PSM_SYSCFG_PSSR1 0x02
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#define PSM_SYSCFG_PSCR1 0x03
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#define PSM_SYSCFG_PSSR2 0x04
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#define PSM_SYSCFG_PSCR2 0x05
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#define PSM_SYSCFG_PSSR3 0x06
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#define PSM_SYSCFG_PSCR3 0x07
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#define PSM_SYSCFG_PSSR(batt,fgr) (fgr & 0x1f ) | \
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((batt & 0x07) << 5)
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#define PSM_SYSCFG_PSCR(e,lo,ti) (ti & 0x0f) | \
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((lo & 0x01) << 6) | \
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((e & 0x01) << 7)
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/* Mode 1 - Battery fuel guage read / write */
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#define PSM_BQRW_CACHED 0x80
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#define PSM_BQRW_REGMASK 0x1f
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/* Mode 2 - Battery control block read / write */
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#define PSM_BCB_BATC0 0x00
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#define PSM_BCB_BATC1 0x01
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#define PSM_BCB_BATC2 0x02
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#define PSM_BCB_BATC3 0x03
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#define PSM_BCB_BATC4 0x04
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#define PSM_BCB_CR 0x01 /* Calibration required */
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#define PSM_BCB_BCF 0x02 /* Battery control block failure */
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#define PSM_BCB_FGF 0x04 /* Fuel guage failure */
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#define PSM_BCB_FULL 0x08 /* Battery is full */
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#define PSM_BCB_CHG 0x10 /* Battery pack charging */
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#define PSM_BCB_USE 0x20 /* Battery pack in use */
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#define PSM_BCB_E 0x40 /* Battery pack enabled */
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#define PSM_BCB_IN 0x80 /* Battery pack in use */
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/* Mode 4 - Miscellaneous control/status registers */
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#define PSM_MISC_HVER 0x00 /* Hardware version number */
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#define PSM_MISC_FVER 0x01 /* Firmware version number */
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#define PSM_MISC_BLITE 0x10 /* Backlight intensity register */
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#define PSM_MISC_IMR 0x20 /* Interrupt mask register */
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#define PSM_MISC_UPS 0x21 /* UPS battery pack number */
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#define PSM_MISC_FMTA 0x30 /* Battery format registers */
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#define PSM_MISC_FMTB 0x31 /* Battery format registers */
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#define PSM_MISC_FMTC 0x32 /* Battery format registers */
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#define PSM_MISC_FMTD 0x33 /* Battery format registers */
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#define PSM_MISC_FAN0 0x40 /* Fan control */
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#define PSM_MISC_FAN1 0x41 /* Fan control */
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#define PSM_MISC_FAN2 0x42 /* Fan control */
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#define PSM_MISC_FAN3 0x43 /* Fan control */
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#define PSM_MISC_FAN4 0x44 /* Fan control */
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#define PSM_MISC_AD0 0x50 /* Processor internal thermal */
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#define PSM_MISC_AD1 0x51 /* Processor vicinity thermal */
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#define PSM_MISC_AD2 0x52 /* Processor case thermal */
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#define PSM_MISC_AD3 0x53 /* Clamshell ambient thermal */
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#define PSM_MISC_AD4 0x54 /* Reserved */
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#define PSM_MISC_AD5 0x55 /* Reserved */
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#define PSM_MISC_AD6 0x56 /* Reserved */
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#define PSM_MISC_AD7 0x57 /* Discharge bus voltage */
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#define PSM_MISC_XMON 0x60 /* External monitor */
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#define PSM_MISC_PCYCLE 0x70 /* Power cycle */
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#define PSM_MISC_ERROR0 0x80
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#define PSM_MISC_ERROR1 0x81
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#define PSM_MISC_PEM 0x90
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#define PSM_MISC_PEMAD0 0xa0
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#define PSM_MISC_PEMAD1 0xa1
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#define PSM_MISC_PEMAD2 0xa2
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#define PSM_MISC_PEMAD3 0xa3
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/* Masks */
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#define PSM_FAN_MASK 0x1f /* 0-31 */
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/* Interrupt mask register defenitions */
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#define PSM_IMR_MBCC 0x40 /* Battery config change interrupt */
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#define PSM_IMR_MTMP 0x20 /* Over temp interrupt */
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#define PSM_IMR_MLIDC 0x10 /* Lid close interrupt */
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#define PSM_IMR_MLIDO 0x08 /* Lid close interrupt */
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#define PSM_IMR_MD 0x04 /* Dock/undock interrupts */
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#define PSM_IMR_MPS 0x01 /* Master power switch interrupt */
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#define PSM_IMR_ALL PSM_IMR_MBCC|PSM_IMR_MTMP|PSM_IMR_MLIDO|PSM_IMR_MLIDC \
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|PSM_IMR_MD|PSM_IMR_MPS
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/* Battery information */
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#define PSM_MAX_BATTERIES 1
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#define PSM_VBATT 11100 /* 11.1v nominal battery voltage */
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#endif /* PSMREG_H */
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