232 lines
6.6 KiB
C
232 lines
6.6 KiB
C
/* $NetBSD: if_qtreg.h,v 1.5 2005/12/11 12:23:29 christos Exp $ */
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/*
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* Copyright (c) 1992 Steven M. Schultz
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* @(#)if_qtreg.h 1.0 (GTE) 10/12/92
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*/
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/*
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* Modification History
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* 26 Feb 93 -- sms
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* Add defines for number of receive and transmit ring descriptors.
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*
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* 12 Oct 92 -- Steven M. Schultz (sms)
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* Created from the DELQA-PLUS Addendum to the DELQA User's Guide.
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*/
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#define QT_MAX_RCV 32
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#define QT_MAX_XMT 12
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/* Receive ring descriptor and bit/field definitions */
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struct qt_rring
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{
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short rmd0;
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short rmd1;
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short rmd2;
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short rmd3;
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short rmd4;
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short rmd5;
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#ifdef pdp11
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struct qt_uba *rhost0;
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short rhost1;
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#else
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short pad1, pad2;
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#endif
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};
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#define RMD0_ERR3 0x4000 /* Error summary. FRA|CRC|OFL|BUF */
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#define RMD0_FRA 0x2000 /* Framing error */
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#define RMD0_OFL 0x1000 /* Overflow error. Oversized packet */
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#define RMD0_CRC 0x0800 /* CRC error */
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#define RMD0_BUF 0x0400 /* Internal device buffer error */
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#define RMD0_STP 0x0200 /* Start of packet */
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#define RMD0_ENP 0x0100 /* End of packet */
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#define RMD1_MCNT 0x0fff /* Message byte count */
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#define RMD2_ERR4 0x8000 /* Error summary. BBL|CER|MIS */
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#define RMD2_BBL 0x4000 /* Babble error on transmit */
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#define RMD2_CER 0x2000 /* Collision error on transmit */
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#define RMD2_MIS 0x1000 /* Packet lost on receive */
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#define RMD2_EOR 0x0800 /* End of receive ring */
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#define RMD2_RON 0x0020 /* Receiver on */
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#define RMD2_TON 0x0010 /* Transmitter on */
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#define RMD3_OWN 0x8000 /* Ownership field. */
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#define RMD4_LADR 0xfff8 /* Octabyte aligned low address bits */
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#define RMD5_HADR 0x003f /* High 6 bits of buffer address */
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#define RMD0_BITS "\010\016FRA\015OFL\014CRC\013BUF\012STP\011ENP"
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#define RMD2_BITS "\010\017BBL\014CER\013MIS\012EOR\06RON\05TON"
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/* Transmit ring descriptor and bit/field definitions */
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struct qt_tring
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{
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short tmd0;
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short tmd1;
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short tmd2;
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short tmd3;
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short tmd4;
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short tmd5;
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#ifdef pdp11
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struct qt_uba *thost0;
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short thost1;
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#else
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short pad1, pad2;
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#endif
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};
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#define TMD0_ERR1 0x4000 /* Error summary. LCO|LCA|RTR */
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#define TMD0_MOR 0x1000 /* More than one retry on transmit */
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#define TMD0_ONE 0x0800 /* One retry on transmit */
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#define TMD0_DEF 0x0400 /* Deferral during transmit */
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#define TMD1_LCO 0x1000 /* Late collision on transmit */
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#define TMD1_LCA 0x0800 /* Loss of carrier on transmit */
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#define TMD1_RTR 0x0400 /* Retry error on transmit */
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#define TMD1_TDR 0x03ff /* Time Domain Reflectometry value */
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#define TMD2_ERR2 0x8000 /* Error summary. BBL|CER|MIS */
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#define TMD2_BBL 0x4000 /* Babble error on transmit */
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#define TMD2_CER 0x2000 /* Collision error on transmit */
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#define TMD2_MIS 0x1000 /* Packet lost on receive */
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#define TMD2_EOR 0x0800 /* Endof Receive ring reached */
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#define TMD2_RON 0x0020 /* Receiver on */
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#define TMD2_TON 0x0010 /* Transmitter on */
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#define TMD3_OWN 0x8000 /* Ownership field */
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#define TMD3_FOT 0x4000 /* First of two flag */
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#define TMD3_BCT 0x0fff /* Byte count */
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#define TMD4_LADR 0xfff8 /* Octabyte aligned low address bits */
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#define TMD5_HADR 0x003f /* High 6 bits of buffer address */
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#define TMD1_BITS "\010\015LCO\014LCA\013RTR"
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#define TMD2_BITS "\010\017BBL\016CER\015MIS\014EOR\06RON\05TON"
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/* DELQA-YM CSR layout */
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#ifdef notdef
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struct qtcsr0
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{
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short Ibal;
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short Ibah;
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short Icr;
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short pad0;
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short Srqr;
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short pad1;
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};
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struct qtdevice
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{
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union {
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u_char Sarom[12];
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struct qtcsr0 csr0;
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} qt_un0;
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short srr;
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short arqr;
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};
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#define ibal qt_un0.csr0.Ibal
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#define ibah qt_un0.csr0.Ibah
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#define srqr qt_un0.csr0.Srqr
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#define icr qt_un0.csr0.Icr
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#define sarom qt_un0.Sarom
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#endif
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#define CSR_IBAL 0
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#define CSR_IBAH 2
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#define CSR_ICR 4
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#define CSR_SRQR 8
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#define CSR_SRR 12
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#define CSR_ARQR 14
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/* SRR definitions */
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#define SRR_FES 0x8000
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#define SRR_CHN 0x4000
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#define SRR_NXM 0x1000
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#define SRR_PER 0x0800
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#define SRR_IME 0x0400
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#define SRR_TBL 0x0200
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#define SRR_RESP 0x0003
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#define SRR_BITS "\010\017CHN\015NXM\014PER\013IME\012TBL"
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/* SRQR definitions */
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#define SRQR_REQ 0x0003
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/* ARQR definitions */
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#define ARQR_TRQ 0x8000
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#define ARQR_RRQ 0x0080
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#define ARQR_SR 0x0002
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/* define ICR definitions */
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#define ICR_CMD 0x0001
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/* DELQA registers used to shift into -T mode */
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#ifdef notdef
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#define xcr0 qt_un0.csr0.Ibal
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#define xcr1 qt_un0.csr0.Ibah
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#endif
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#define CSR_XCR0 CSR_IBAL
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#define CSR_XCR1 CSR_IBAH
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/* INIT block structure and definitions */
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struct qt_init
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{
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short mode;
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u_char paddr[6]; /* 48 bit physical address */
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u_char laddr[8]; /* 64 bit logical address filter */
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u_short rx_lo; /* low 16 bits of receive ring addr */
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u_short rx_hi; /* high 6 bits of receive ring addr */
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u_short tx_lo; /* low 16 bits of transmit ring addr */
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u_short tx_hi; /* high 6 bits of transmit ring addr */
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u_short options;
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u_short vector;
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u_short hit;
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char passwd[6];
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char pad[4]; /* even on 40 byte for alignment */
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};
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#define INIT_MODE_PRO 0x8000 /* Promiscuous mode */
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#define INIT_MODE_INT 0x0040 /* Internal Loopback */
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#define INIT_MODE_DRT 0x0020 /* Disable Retry */
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#define INIT_MODE_DTC 0x0008 /* Disable Transmit CRC */
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#define INIT_MODE_LOP 0x0004 /* Loopback */
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#define INIT_OPTIONS_HIT 0x0002 /* Host Inactivity Timeout Flag */
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#define INIT_OPTIONS_INT 0x0001 /* Interrupt Enable Flag */
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