91 lines
3.2 KiB
C++
91 lines
3.2 KiB
C++
/* -*-C++-*- $NetBSD: mips_vr41.h,v 1.1 2001/02/09 18:35:07 uch Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <hpcboot.h>
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#include <mips/mips_arch.h>
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class VR41XX : public MIPSArchitecture {
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private:
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public:
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VR41XX(Console *&, MemoryManager *&);
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~VR41XX(void);
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virtual BOOL init(void);
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virtual void systemInfo(void);
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virtual void cacheFlush(void);
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static void boot_func(struct BootArgs *, struct PageTag *);
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};
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#define MIPS_VR41XX_CACHE_FLUSH() \
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__asm( \
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".set noreorder;" \
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/* Flush I-cache */ \
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"li t0, 0x80000000;" \
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"addu t1, t0, 1024*128;" \
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"subu t1, t1, 128;" \
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"1:" \
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"cache 0, 0(t0);" \
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"cache 0, 16(t0);" \
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"cache 0, 32(t0);" \
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"cache 0, 48(t0);" \
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"cache 0, 64(t0);" \
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"cache 0, 80(t0);" \
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"cache 0, 96(t0);" \
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"cache 0, 112(t0);" \
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"bne t0, t1, 1b;" \
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"addu t0, t0, 128;" \
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\
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/* Flush D-cache */ \
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"li t0, 0x80000000;" \
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"addu t1, t0, 1024*128;" \
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"subu t1, t1, 128;" \
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"2:" \
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"cache 1, 0(t0);" \
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"cache 1, 16(t0);" \
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"cache 1, 32(t0);" \
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"cache 1, 48(t0);" \
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"cache 1, 64(t0);" \
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"cache 1, 80(t0);" \
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"cache 1, 96(t0);" \
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"cache 1, 112(t0);" \
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"bne t0, t1, 2b;" \
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"addu t0, t0, 128;" \
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".set reorder;" \
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)
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