145 lines
10 KiB
C++
145 lines
10 KiB
C++
/* -*-C++-*- $NetBSD: machine_config.cpp,v 1.4 2001/05/16 11:13:20 enami Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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//
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// Platform dependent configuration.
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//
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#include <hpcmenu.h>
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#include <machine/bootinfo.h>
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#include <machine/platid.h>
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#include <machine/platid_mask.h>
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#include <framebuffer.h>
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//
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// Frame buffer information.
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//
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struct FrameBufferInfo::framebuffer_info
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FrameBufferInfo::_table[] =
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{
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// CPU MACHINE BPP WIDTH HEIGHT LINEBYTES FRAME BUFFER ADDR
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#ifdef MIPS
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// VR41 (kseg1 address)
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{ PLATID_CPU_MIPS_VR_4102, PLATID_MACH_EVEREX_FREESTYLE_AXX , 2, 240, 320, 80, 0xaa000000 },
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{ PLATID_CPU_MIPS_VR_4102, PLATID_MACH_NEC_MCCS_11 , 2, 480, 240, 256, 0xaa000000 },
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{ PLATID_CPU_MIPS_VR_4102, PLATID_MACH_NEC_MCCS_12 , 2, 480, 240, 256, 0xaa000000 },
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{ PLATID_CPU_MIPS_VR_4102, PLATID_MACH_NEC_MCCS_13 , 2, 480, 240, 256, 0xaa000000 },
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{ PLATID_CPU_MIPS_VR_4102, PLATID_MACH_NEC_MCR_MPRO700 , 2, 640, 240, 256, 0xaa000000 },
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{ PLATID_CPU_MIPS_VR_4111, PLATID_MACH_CASIO_CASSIOPEIAE_E55 , 2, 240, 320, 256, 0xaa000000 },
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{ PLATID_CPU_MIPS_VR_4111, PLATID_MACH_COMPAQ_AERO_1530 , 2, 240, 320, 0, 0xa0000000 },
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{ PLATID_CPU_MIPS_VR_4111, PLATID_MACH_COMPAQ_PRESARIO_213 , 8, 240, 320, 0, 0xa0000000 },
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{ PLATID_CPU_MIPS_VR_4111, PLATID_MACH_NEC_MCR_300 , 2, 640, 240, 256, 0xaa000000 },
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{ PLATID_CPU_MIPS_VR_4111, PLATID_MACH_NEC_MCR_500 , 8, 640, 240, 1024, 0xb3000000 },
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{ PLATID_CPU_MIPS_VR_4111, PLATID_MACH_NEC_MCR_500A , 8, 640, 240, 1024, 0xb3000000 },
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{ PLATID_CPU_MIPS_VR_4111, PLATID_MACH_NEC_MCR_FORDOCOMO , 2, 640, 240, 256, 0xaa000000 },
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{ PLATID_CPU_MIPS_VR_4111, PLATID_MACH_SHARP_TRIPAD_PV6000 , 8, 640, 480, 640, 0xaa000000 },
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{ PLATID_CPU_MIPS_VR_4121, PLATID_MACH_CASIO_CASSIOPEIAE_E100 , 16, 240, 320, 512, 0xaa200000 },
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{ PLATID_CPU_MIPS_VR_4121, PLATID_MACH_CASIO_CASSIOPEIAE_E500 , 16, 240, 320, 512, 0xaa200000 },
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{ PLATID_CPU_MIPS_VR_4121, PLATID_MACH_CASIO_POCKETPOSTPET_POCKETPOSTPET, 16, 320, 240, 1024, 0xaa200000 },
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{ PLATID_CPU_MIPS_VR_4121, PLATID_MACH_FUJITSU_INTERTOP_IT300 , 8, 640, 480, 640, 0xaa000000 },
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{ PLATID_CPU_MIPS_VR_4121, PLATID_MACH_FUJITSU_INTERTOP_IT300 , 16, 640, 480, 1280, 0xaa000000 },
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{ PLATID_CPU_MIPS_VR_4121, PLATID_MACH_FUJITSU_INTERTOP_IT310 , 8, 640, 480, 640, 0xaa000000 },
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{ PLATID_CPU_MIPS_VR_4121, PLATID_MACH_IBM_WORKPAD_26011AU , 16, 640, 480, 1280, 0xaa000000 },
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{ PLATID_CPU_MIPS_VR_4121, PLATID_MACH_NEC_MCR_320 , 2, 640, 240, 160, 0xaa000000 },
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{ PLATID_CPU_MIPS_VR_4121, PLATID_MACH_NEC_MCR_330 , 2, 640, 240, 160, 0xaa000000 },
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{ PLATID_CPU_MIPS_VR_4121, PLATID_MACH_NEC_MCR_430 , 16, 640, 240, 1280, 0xaa180100 },
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{ PLATID_CPU_MIPS_VR_4121, PLATID_MACH_NEC_MCR_510 , 8, 640, 240, 1024, 0xaa000000 },
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{ PLATID_CPU_MIPS_VR_4121, PLATID_MACH_NEC_MCR_510 , 16, 640, 240, 1600, 0xaa000000 },
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{ PLATID_CPU_MIPS_VR_4121, PLATID_MACH_NEC_MCR_520 , 16, 640, 240, 1600, 0xaa000000 },
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{ PLATID_CPU_MIPS_VR_4121, PLATID_MACH_NEC_MCR_520A , 16, 640, 240, 1600, 0xaa000000 },
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{ PLATID_CPU_MIPS_VR_4121, PLATID_MACH_NEC_MCR_530 , 8, 640, 240, 640, 0xaa1d4c00 },
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{ PLATID_CPU_MIPS_VR_4121, PLATID_MACH_NEC_MCR_530 , 16, 640, 240, 1280, 0xaa180100 },
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{ PLATID_CPU_MIPS_VR_4121, PLATID_MACH_NEC_MCR_530A , 16, 640, 240, 1280, 0xaa180100 },
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{ PLATID_CPU_MIPS_VR_4121, PLATID_MACH_NEC_MCR_700 , 16, 800, 600, 1600, 0xaa000000 },
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{ PLATID_CPU_MIPS_VR_4121, PLATID_MACH_NEC_MCR_700A , 16, 800, 600, 1600, 0xaa000000 },
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{ PLATID_CPU_MIPS_VR_4121, PLATID_MACH_NEC_MCR_730 , 16, 800, 600, 1600, 0xaa0ea600 },
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{ PLATID_CPU_MIPS_VR_4121, PLATID_MACH_NEC_MCR_730A , 16, 800, 600, 1600, 0xaa0ea600 },
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{ PLATID_CPU_MIPS_VR_4121, PLATID_MACH_NEC_MCR_SIGMARION , 16, 640, 240, 1280, 0xaa000000 },
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{ PLATID_CPU_MIPS_VR_4121, PLATID_MACH_SHARP_TRIPAD_PV6000 , 16, 640, 480, 1280, 0xaa200000 },
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{ PLATID_CPU_MIPS_VR_4121, PLATID_MACH_FUJITSU_PENCENTRA_130 , 8, 640, 480, 640, 0xb0201e00 },
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{ PLATID_CPU_MIPS_VR_4122, PLATID_MACH_VICTOR_INTERLINK_MPC303 , 16, 800, 600, 0, 0x00000000 },
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// TX39 (can't determine frame buffer address)
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{ PLATID_CPU_MIPS_TX_3912, PLATID_MACH_COMPAQ_C_2010 , 8, 640, 240, 0, 0x00000000 },
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{ PLATID_CPU_MIPS_TX_3912, PLATID_MACH_COMPAQ_C_2015 , 8, 640, 240, 0, 0x00000000 },
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{ PLATID_CPU_MIPS_TX_3912, PLATID_MACH_COMPAQ_C_810 , 2, 640, 240, 0, 0x00000000 },
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{ PLATID_CPU_MIPS_TX_3912, PLATID_MACH_PHILIPS_NINO_312 , 2, 240, 320, 0, 0x00000000 },
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{ PLATID_CPU_MIPS_TX_3912, PLATID_MACH_SHARP_MOBILON_HC1200 , 4, 640, 240, 0, 0x00000000 },
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{ PLATID_CPU_MIPS_TX_3912, PLATID_MACH_SHARP_MOBILON_HC4100 , 4, 640, 240, 0, 0x00000000 },
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{ PLATID_CPU_MIPS_TX_3922, PLATID_MACH_SHARP_TELIOS_HCAJ1 , 16, 800, 600, 0, 0x00000000 },
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{ PLATID_CPU_MIPS_TX_3922, PLATID_MACH_SHARP_TELIOS_HCVJ1C_JP , 16, 800, 480, 0, 0x00000000 },
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{ PLATID_CPU_MIPS_TX_3922, PLATID_MACH_VICTOR_INTERLINK_MPC101 , 16, 640, 480, 0, 0x00000000 },
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#endif // MIPS
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#ifdef SHx
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// SH7709 (P2 address)
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{ PLATID_CPU_SH_3_7709 , PLATID_MACH_HP_LX_620 , 8, 640, 240, 640, 0xb2000000 },
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{ PLATID_CPU_SH_3_7709 , PLATID_MACH_HP_LX_620JP , 8, 640, 240, 640, 0xb2000000 },
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{ PLATID_CPU_SH_3_7709 , PLATID_MACH_HITACHI_PERSONA_HPW50PAD , 8, 640, 240, 640, 0xb2000000 },
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{ PLATID_CPU_SH_3_7709 , PLATID_MACH_HITACHI_PERSONA_HPW230JC , 8, 640, 240, 640, 0xb2000000 },
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// SH7709A (P2 address)
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{ PLATID_CPU_SH_3_7709A , PLATID_MACH_HP_JORNADA , 16, 640, 240, 1280, 0xb2000000 },
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#endif // SHx
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#ifdef ARM
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// SA-1100 (can't determine frame buffer address)
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{ PLATID_CPU_ARM_STRONGARM_SA1100 , PLATID_MACH_HP_JORNADA_820 , 8, 640, 480, 0, 0x00000000 },
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{ PLATID_CPU_ARM_STRONGARM_SA1100 , PLATID_MACH_HP_JORNADA_820JP , 8, 640, 480, 0, 0x00000000 },
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// SA-1110
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{ PLATID_CPU_ARM_STRONGARM_SA1110 , PLATID_MACH_HP_JORNADA_720 , 16, 640, 240, 0, 0x00000000 },
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{ PLATID_CPU_ARM_STRONGARM_SA1110 , PLATID_MACH_HP_JORNADA_720JP , 16, 640, 240, 1280, 0x48200000 },
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{ PLATID_CPU_ARM_STRONGARM_SA1110 , PLATID_MACH_COMPAQ_IPAQ_H3600 , 16, 240, 320, 0, 0x00000000 },
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#endif // ARM
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{ 0, 0, 0, 0, 0, 0, 0 } // TERMINATOR
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};
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//
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// Unsupported machine list.
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//
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struct HpcMenuInterface::support_status
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HpcMenuInterface::_unsupported[] =
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{
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#ifdef ARM
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#endif // ARM
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#ifdef MIPS
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#endif // MIPS
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#ifdef SHx
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{ PLATID_CPU_SH_4_7750 , PLATID_MACH_HITACHI_PERSONA_HPW650PA , L"SH4 CPU not supported yet." },
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{ PLATID_CPU_SH_3_7709 , PLATID_MACH_CASIO_CASSIOPEIAA_A55V , L"unknown Companion Chip FM-7403" },
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#endif // SHx
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{ 0, 0, 0 } // TERMINATOR
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};
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