180 lines
8.9 KiB
C
180 lines
8.9 KiB
C
/* $NetBSD: mvsdioreg.h,v 1.1 2010/09/23 12:36:01 kiyohara Exp $ */
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/*
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* Copyright (c) 2010 KIYOHARA Takashi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MVSDIOREG_H_
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#define _MVSDIOREG_H_
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#define MVSDIO_SIZE 0x10000
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#define MVSDIO_MAX_CLOCK (50 * 1000) /* 50,000 kHz */
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#define MVSDIO_DMABA16LSB 0x0000 /* DMA Buffer Address 16 LSB */
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#define MVSDIO_DMABA16MSB 0x0004 /* DMA Buffer Address 16 MSB */
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#define MVSDIO_DBS 0x0008 /* Data Block Size */
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#define DBS_BLOCKSIZE_MASK 0xfff
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#define DBS_BLOCKSIZE(s) ((s) & DBS_BLOCKSIZE_MASK)
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#define DBS_BLOCKSIZE_MAX 0x800
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#define MVSDIO_DBC 0x000c /* Data Block Count */
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#define DBC_BLOCKCOUNT_MASK 0xfff
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#define DBC_BLOCKCOUNT(c) ((c) & DBC_BLOCKCOUNT_MASK)
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#define MVSDIO_AC16LSB 0x0010 /* Argument in Command 16 LSB */
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#define MVSDIO_AC16MSB 0x0014 /* Argument in Command 16 MSB */
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#define MVSDIO_TM 0x0018 /* Transfer Mode */
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#define TM_SWWRDATASTART (1 << 0) /* InitWrDataXfer */
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#define TM_HWWRDATAEN (1 << 1) /* SWInitWrDataXfer */
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#define TM_AUTOCMD12EN (1 << 2) /* SWIssuesCMD12 */
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#define TM_INTCHKEN (1 << 3) /* CheckInterrupts */
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#define TM_DATAXFERTOWARDHOST (1 << 4) /* XferDataToSDHost */
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#define TM_STOPCLKEN (1 << 5) /* StopSDClocks */
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#define TM_HOSTXFERMODE (1 << 6) /* SW Write */
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#define MVSDIO_C 0x001c /* Command */
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#define C_RESPTYPE_NR (0 << 0) /* NoResponse */
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#define C_RESPTYPE_136BR (1 << 0) /* 136BitResponse */
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#define C_RESPTYPE_48BR (2 << 0) /* 48BitResponse */
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#define C_RESPTYPE_48BRCB (3 << 0) /*48BitResponseChkBusy*/
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#define C_DATACRC16CHKEN (1 << 2) /* EnableCrc16Chk */
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#define C_CMDCRCCHKEN (1 << 3) /* HCCrcChk */
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#define C_CMDINDEXCHKEN (1 << 4) /* HCChkIndex */
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#define C_DATAPRESENT (1 << 5) /* DataAwaitsTransfer */
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#define C_UNEXPECTEDRESPEN (1 << 7) /* UnexpectedRespEn */
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#define C_CMDINDEX(c) ((c) << 8)
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#define MVSDIO_NRH 8
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#define MVSDIO_RH(n) (0x0020 + ((n) << 2)) /* Response Halfword n */
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#define RH_MASK 0xffff
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#define MVSDIO_16DWACPU 0x0040 /* 16-bit Data Word Accessed by CPU */
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#define MVSDIO_CRC7lR 0x0044 /* CRC7 of l Response */
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#define CRC7lR_CRC7RESPTOKEN_MASK 0x7f
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#define MVSDIO_HPS16LSB 0x0048 /* Host Present State 16 LSB */
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#define HPS16LSB_CMDINHIBITCMD (1 << 0) /* CmdRegWrite */
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#define HPS16LSB_CARDBUSY (1 << 1) /* Card Busy */
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#define HPS16LSB_DATLEVEL(x) (((x) >> 3) & 0xf) /* DAT[3:0] Line Signal Level */
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#define HPS16LSB_CMDLEVEL (1 << 7) /* CMD line Signal Level */
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#define HPS16LSB_TXACTIVE (1 << 8) /* TxEnabled */
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#define HPS16LSB_RXACTIVE (1 << 9) /* RxDisabled */
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#define HPS16LSB_FIFOFULL (1 << 12) /* FIFO Full */
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#define HPS16LSB_FIFOEMPTY (1 << 13) /* FIFO Empty */
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#define HPS16LSB_AUTOCMD12ACTIVE (1 << 14) /*auto_cmd12 is active*/
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#define MVSDIO_HC 0x0050 /* Host Control */
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#define HC_PUSHPULLEN (1 << 0) /* PushPullEn */
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#define HC_CARDTYPE_MASK (3 << 1) /* Card type */
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#define HC_CARDTYPE_MEMORYONLY (0 << 1) /* Mem only SD card */
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#define HC_CARDTYPE_IOONLY (1 << 1) /* IO only SD card */
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#define HC_CARDTYPE_IOMEMCOMBO (2 << 1) /* IO and mem combo */
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#define HC_CARDTYPE_MMC (3 << 1) /* MMC card */
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#define HC_BIGENDIAN (1 << 3) /* BigEndian */
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#define HC_LSBFIRST (1 << 4) /* LSB */
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#define HC_DATAWIDTH (1 << 9) /* Data Width */
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#define HC_HISPEEDEN (1 << 10) /* HighSpeedEnable */
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#define HC_TIMEOUTVALUE_MAX (0xf << 11)
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#define HC_TIMEOUTEN (1 << 15) /* Timeout */
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#define MVSDIO_DBGC 0x0054 /* Data Block Gap Control */
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#define DBGC_STOPATBLOCKGAPREQ (1 << 0) /* Stop at block gap request */
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#define DBGC_CONTREQ (1 << 1) /* Continue request */
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#define DBGC_RDWAITCTL (1 << 2) /* EnableRdWait */
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#define DBGC_STOPDATXFER (1 << 3) /* StopDataXferEn */
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#define DBGC_RESUME (1 << 4)
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#define DBGC_SUSPEND (1 << 5)
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#define MVSDIO_CC 0x0058 /* Clock Control */
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#define CC_SCLKMASTEREN (1 << 0) /* SdclkEn */
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#define MVSDIO_SR 0x005c /* Software Reset */
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#define SR_SWRESET (1 << 8)
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#define MVSDIO_NIS 0x0060 /* Normal Interrupt Status */
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#define MVSDIO_NISE 0x0068 /* Normal Interrupt Status Enable */
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#define MVSDIO_NISIE 0x0070 /* Normal Intr Status Intr Enable */
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#define NIS_CMDCOMPLETE (1 << 0) /* Command Complete */
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#define NIS_XFERCOMPLETE (1 << 1) /* Transfer Complete */
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#define NIS_BLOCKGAPEV (1 << 2) /* Block gap event */
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#define NIS_DMAINT (1 << 3) /* DMA interrupt */
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#define NIS_TXRDY (1 << 4)
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#define NIS_RXRDY (1 << 5)
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#define NIS_CARDINT (1 << 8) /* Card interrupt */
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#define NIS_READWAITON (1 << 9) /* Read Wait state is on */
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#define NIS_IMBFIFO8WFULL (1 << 10)
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#define NIS_IMBFIFO8WAVAIL (1 << 11)
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#define NIS_SUSPENSEON (1 << 12)
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#define NIS_AUTOCMD12COMPLETE (1 << 13) /* Auto_cmd12 is comp */
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#define NIS_UNEXPECTEDRESPDET (1 << 14)
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#define NIS_ERRINT (1 << 15) /* Error interrupt */
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#define MVSDIO_EIS 0x0064 /* Error Interrupt Status */
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#define MVSDIO_EISE 0x006c /* Error Interrupt Status Enable */
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#define MVSDIO_EISIE 0x0074 /* Error Intr Status Interrupt Enable */
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#define EIS_CMDTIMEOUTERR (1 << 0) /*Command timeout err*/
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#define EIS_CMDCRCERR (1 << 1) /* Command CRC Error */
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#define EIS_CMDENDBITERR (1 << 2) /*Command end bit err*/
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#define EIS_CMDINDEXERR (1 << 3) /*Command Index Error*/
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#define EIS_DATATIMEOUTERR (1 << 4) /* Data timeout error */
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#define EIS_RDDATACRCERR (1 << 5) /* Read data CRC err */
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#define EIS_RDDATAENDBITERR (1 << 6) /*Rd data end bit err*/
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#define EIS_AUTOCMD12ERR (1 << 8) /* Auto CMD12 error */
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#define EIS_CMDSTARTBITERR (1 << 9) /*Cmd start bit error*/
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#define EIS_XFERSIZEERR (1 << 10) /*Tx size mismatched err*/
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#define EIS_RESPTBITERR (1 << 11) /* Response T bit err */
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#define EIS_CRCENDBITERR (1 << 12) /* CRC end bit error */
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#define EIS_CRCSTARTBITERR (1 << 13) /* CRC start bit err */
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#define EIS_CRCSTATERR (1 << 14) /* CRC status error */
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#define MVSDIO_ACMD12IS 0x0078 /* Auto CMD12 Interrupt Status */
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#define ACMD12IS_AUTOCMD12NOTEXE (1 << 0)
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#define ACMD12IS_AUTOCMD12TIMEOUTER (1 << 1)
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#define ACMD12IS_AUTOCMD12CRCER (1 << 2)
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#define ACMD12IS_AUTOCMD12ENDBITER (1 << 3)
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#define ACMD12IS_AUTOCMD12INDEXER (1 << 4)
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#define ACMD12IS_AUTOCMD12RESPTBITER (1 << 5)
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#define ACMD12IS_AUTOCMD12RESPSTARTBITER (1 << 6)
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#define MVSDIO_CNBRDB 0x007c/*Current Num of Bytes Remaining in Data*/
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#define MVSDIO_CNDBLBT 0x0080/*Current Num of Data Blk Left ToBe Txed*/
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#define MVSDIO_AACC16LSBT 0x0084 /*Arg in Auto Cmd12 Command 16 LSB Txed*/
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#define MVSDIO_AACC16MSBT 0x0088 /*Arg in Auto Cmd12 Command 16 MSB Txed*/
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#define MVSDIO_IACCT 0x008c /* Index of Auto Cmd12 Commands Tx-ed */
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#define IACCT_AUTOCMD12BUSYCHKEN (1 << 0)
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#define IACCT_AUTOCMD12INDEXCHKEN (1 << 1)
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#define IACCT_AUTOCMD12INDEX (MMC_STOP_TRANSMISSION << 8)
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#define MVSDIO_ACRH(n) (0x0090 + ((n) << 2)) /* Auto Cmd12 Response Halfword n */
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#define MVSDIO_MCL 0x0100 /* Mbus Control Low */
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#define MVSDIO_MCH 0x0104 /* Mbus Control High */
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#define MCL_SDARBENTRY(n, x) (((x) & 0xf) << ((n) << 2))
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#define MVSDIO_NWINDOW 4
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#define MVSDIO_WC(n) (0x0108 + ((n) << 3)) /* Window n Control */
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#define WC_WINEN (1 << 0) /* Window n Enable */
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#define WC_TARGET(t) (((t) & 0xf) << 4)
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#define WC_ATTR(a) (((a) & 0xff) << 8)
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#define WC_SIZE(s) (((s) - 1) & 0xffff0000)
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#define MVSDIO_WB(n) (0x010c + ((n) << 3)) /* Window n Base */
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#define WB_BASE(b) ((b) & 0xffff0000)
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#define MVSDIO_CDV 0x0128 /* Clock Divider Value */
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#define CDV_CLKDVDRMVALUE_MASK 0x7ff
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#define MVSDIO_ADE 0x012c /* Address Decoder Error */
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#define ADE_ADD_DEC_MISS_ERR (1 << 0)
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#define ADE_ADD_DEC_MULTI_ERR (1 << 1)
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#define MVSDIO_ADEM 0x0130 /* Address Decoder Error Mask */
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#define ADEM_VARIOUS(x) ((x) << 0) /* Do not mask */
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#endif /* _MVSDIOREG_H_ */
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