139 lines
4.6 KiB
C
139 lines
4.6 KiB
C
/* $NetBSD: bcm53xx_intr.h,v 1.1 2012/09/01 00:04:44 matt Exp $ */
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/*-
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_BROADCOM_BCM53XX_INTR_H_
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#define _ARM_BROADCOM_BCM53XX_INTR_H_
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#define PIC_MAXSOURCES 256
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#define PIC_MAXMAXSOURCES 280
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/*
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* The BCM53xx uses a generic interrupt controller so pull that stuff.
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*/
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#include <arm/cortex/gic_intr.h>
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#include <arm/cortex/a9tmr_intr.h> /* A9 Timer PPIs */
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#define IRQ_L2CC 32
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#define IRQ_PWRWDOG 33
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#define IRQ_TRAP8 34
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#define IRQ_TRAP1 35
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#define IRQ_COMMTX 36
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#define IRQ__RSVD37 37
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#define IRQ_COMMRX 38
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#define IRQ__RSVD39 39
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#define IRQ_PMU 40
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#define IRQ__RSVD41 41
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#define IRQ_CTI 42
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#define IRQ__RSVD43 43
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#define IRQ_DEFLAG_CPU0 44
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#define IRQ_DEFLAG_CPU1 45
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#define IRQ_ARMCORE_M1_PINS_BUS 46
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#define IRQ_PCIE0_M0_PINS_BUS 47
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#define IRQ_PCIE1_M0_PINS_BUS 48
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#define IRQ_PCIE2_M0_PINS_BUS 49
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#define IRQ_DMA_M0_PINS_BUS 50
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#define IRQ_AMAC_M0_PINS_BUS 51
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#define IRQ_AMAC_M1_PINS_BUS 52
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#define IRQ_AMAC_M2_PINS_BUS 53
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#define IRQ_AMAC_M3_PINS_BUS 54
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#define IRQ_USBH_M0_PINS_BUS 55
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#define IRQ_USBH_M1_PINS_BUS 56
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#define IRQ_SDIO_M0_PINS_BUS 57
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#define IRQ_I2S_M0_PINS_BUS 58
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#define IRQ_A9JTAG_M0_PINS_BUS 59
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#define IRQ_JTAG_M0_PINS_BUS 60
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#define IRQ_ARMCORE_ACP_PINS_BUS 61
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#define IRQ_ARMCORE_S0_PINS_BUS 62
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#define IRQ_DDR_S1_PINS_BUS 63
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#define IRQ_DDR_S2_PINS_BUS 64
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#define IRQ_PCIE0_S0_PINS_BUS 65
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#define IRQ_PCIE1_S0_PINS_BUS 66
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#define IRQ_PCIE2_S0_PINS_BUS 67
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#define IRQ_ROM_S0_PINS_BUS 68
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#define IRQ_NAND_S0_PINS_BUS 69
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#define IRQ_QSPI_S0_PINS_BUS 70
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#define IRQ_A9JTAG_S0_PINS_BUS 71
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#define IRQ_APBX_S0_PINS_BUS 72
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#define IRQ_DS_0_PINS_BUS 73
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#define IRQ_DS_1_PINS_BUS 74
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#define IRQ_DS_2_PINS_BUS 75
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#define IRQ_DS_3_PINS_BUS 76
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#define IRQ_DS_4_PINS_BUS 77
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#define IRQ_DDR_CONTROLLER 78
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#define IRQ_DMAC 79 /* 16 */
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#define IRQ_DMAC_ABORT 95
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#define IRQ_NAND_RD_MISS 96
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#define IRQ_NAND_BLK_ERASE_COMP 97
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#define IRQ_NAND_COPY_BACK_COMP 98
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#define IRQ_NAND_PGM_PAGE_COMP 99
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#define IRQ_NAND_RO_CTLR_READY 100
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#define IRQ_NAND_RB_B 101
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#define IRQ_NAND_ECC_MIPS_UNCORR 102
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#define IRQ_NAND_ECC_MIPS_CORR 103
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#define IRQ_SPI_FULLNESS_REACHED 104
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#define IRQ_SPI_TRUNCATED 105
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#define IRQ_SPI_IMPATIENT 106
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#define IRQ_SPI_SESSION_DONE 107
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#define IRQ_SPI_INTERRUPT_OVERREAD 108
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#define IRQ_SPI_MSPI_INTERRUPT_DONE 109
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#define IRQ_SPI_MSPI_INTERRUPT_HALT_SET_TRANSACTION_DONE 110
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#define IRQ_USB2 111
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#define IRQ_XHCI_0 112
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#define IRQ_XHCI_1 113
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#define IRQ_XHCI_2 114
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#define IRQ_XHCI_3 115
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#define IRQ_XHCI_HSE 116
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#define IRQ_CCA 117
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#define IRQ_UART2 118
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#define IRQ_RSVD119 119
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#define IRQ_I2S 120
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#define IRQ_SMBUS 121
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#define IRQ_TIMER0_1 122
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#define IRQ_TIMER0_2 123
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#define IRQ_TIMER1_1 124
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#define IRQ_TIMER1_2 125
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#define IRQ_RNG 126
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#define IRQ_SWITCH_SOC 127 /* 32 */
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#define IRQ_NETWORK_LINK_EVENT 127 /* 8 */
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#define IRQ_PHY 135
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#define IRQ_TIMESYNC 136
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#define IRQ_IMP_SLEEP_TIMER 137 /* 3 */
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#define IRQ_PCIE_INT0 159 /* 6 */
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#define IRQ_PCIE_INT1 165 /* 6 */
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#define IRQ_PCIE_INT2 171 /* 6 */
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#define IRQ_SDIO 177
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#define IRQ_FA 178
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#define IRQ_GMAC0 179
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#define IRQ_GMAC1 180
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#define IRQ_GMAC2 181
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#define IRQ_GMAC3 182
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#endif /* _ARM_BROADCOM_BC53XX_INTR_H_ */
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