116 lines
3.9 KiB
C
116 lines
3.9 KiB
C
/* $NetBSD: rmixl_intr.h,v 1.3 2011/04/14 05:16:28 cliff Exp $ */
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/*-
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* Copyright (c) 2010 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Cliff Neighbors.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MIPS_RMI_RMIXL_INTR_H_
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#define _MIPS_RMI_RMIXL_INTR_H_
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#ifdef _KERNEL_OPT
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#include "opt_multiprocessor.h"
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#endif
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/*
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* A 'vector' is bit number in EIRR/EIMR
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* - non-IRT-based interrupts use vectors 0..31
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* - IRT-based interrupts use vectors 32..63
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* - RMIXL_VECTOR_IRT(vec) is used to index into the IRT
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* - IRT entry n always routes to vector RMIXL_IRT_VECTOR(n)
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* - only 1 intrhand_t per vector
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*/
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#define NINTRVECS 64 /* bit width of the EIRR */
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#define NIRTS 32 /* #entries in the Interrupt Redirection Table */
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/*
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* mapping between IRT index and vector number
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*/
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#define RMIXL_VECTOR_IS_IRT(vec) ((vec) >= 32)
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#define RMIXL_IRT_VECTOR(irt) ((irt) + 32)
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#define RMIXL_VECTOR_IRT(vec) ((vec) - 32)
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/*
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* vectors (0 <= vec < 8) are CAUSE[8..15] (including softintrs and count/compare)
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* vectors (8 <= vec < 31) are for other non-IRT based interrupts
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* we use one for FMN, and each IPI currently gets own vector;
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* if NIPIS >= (32 - 8 - 1), then redesign so IPIs share vector(s)
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*/
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#if NIPIS >= 23
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# error too many IPIs
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#endif
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#define RMIXL_INTRVEC_IPI 8
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#define RMIXL_INTRVEC_FMN (RMIXL_INTRVEC_IPI + NIPIS)
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typedef enum {
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RMIXL_TRIG_NONE=0,
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RMIXL_TRIG_EDGE,
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RMIXL_TRIG_LEVEL,
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} rmixl_intr_trigger_t;
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typedef enum {
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RMIXL_POLR_NONE=0,
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RMIXL_POLR_RISING,
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RMIXL_POLR_HIGH,
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RMIXL_POLR_FALLING,
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RMIXL_POLR_LOW,
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} rmixl_intr_polarity_t;
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/*
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* iv_list and ref count manage sharing of each vector
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*/
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typedef struct rmixl_intrhand {
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int (*ih_func)(void *);
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void *ih_arg;
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int ih_mpsafe; /* true if does not need kernel lock */
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int ih_vec; /* vector is bit number in EIRR/EIMR */
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int ih_ipl; /* interrupt priority */
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int ih_cpumask; /* CPUs which may handle this irpt */
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} rmixl_intrhand_t;
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/*
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* stuff exported from rmixl_spl.S
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*/
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extern const struct splsw rmixl_splsw;
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extern uint64_t ipl_eimr_map[];
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extern void *rmixl_intr_establish(int, int, int,
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rmixl_intr_trigger_t, rmixl_intr_polarity_t,
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int (*)(void *), void *, bool);
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extern void rmixl_intr_disestablish(void *);
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extern void *rmixl_vec_establish(int, int, int,
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int (*)(void *), void *, bool);
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extern void rmixl_vec_disestablish(void *);
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extern const char *rmixl_intr_string(int);
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extern void rmixl_intr_init_cpu(struct cpu_info *);
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extern void rmixl_intr_init_clk(void);
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#ifdef MULTIPROCESSOR
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extern void rmixl_intr_init_ipi(void);
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#endif
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#endif /* _MIPS_RMI_RMIXL_INTR_H_ */
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