249 lines
10 KiB
C
249 lines
10 KiB
C
/* $NetBSD: ka43.h,v 1.3 1998/04/13 12:12:59 ragge Exp $ */
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/*
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* Copyright (c) 1996 Ludd, University of Lule}, Sweden.
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* All rights reserved.
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*
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* This code is derived from software contributed to Ludd by Bertram Barth.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed at Ludd, University of
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* Lule}, Sweden and its contributors.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Definitions for I/O addresses of
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*
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* VAXstation 3100 model 76 (RigelMAX)
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*/
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#define KA43_SIDEX 0x20040004 /* SID extension register */
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#define KA43_CFGTST 0x20020000 /* Configuration and Test register */
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#define KA43_IORESET 0x20020000 /* I/O Reset register */
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#define KA43_ROMGETC 0x20040044
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#define KA43_ROMPUTC 0x20040058
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#define KA43_ROMPUTS 0x2004004C
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#define KA43_CH2_BASE 0x10000000 /* 2nd level cache data area */
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#define KA43_CH2_END 0x1FFFFFFF
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#define KA43_CH2_SIZE 0x10000000
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#define KA43_CT2_BASE 0x21000000 /* 2nd level cache tag area */
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#define KA43_CT2_END 0x2101FFFF
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#define KA43_CT2_SIZE 0x20000
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#define KA43_CH2_CREG 0x21100000 /* 2nd level cache control register */
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#define KA43_ROM_BASE 0x20040000 /* System module ROM */
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#define KA43_ROM_END 0x2007FFFF
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#define KA43_ROM_SIZE 0x40000 /* ??? */
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#define KA43_IVN_BASE 0x20040020 /* Interrupt Vector Numbers */
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#define KA43_IVN_END 0x2004003F
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#define KA43_IVN_SIZE 0x20
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#define KA43_HLTCOD 0x20080000 /* Halt Code Register */
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/* #define KA43_MSER 0x20080004*/ /* Memory System Error register */
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/* #define KA43_MEAR 0x20080008*/ /* Memory Error Address register */
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#define KA43_INTMSK 0x2008000C /* Interrupt Mask register */
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#define KA43_VDCORG 0x2008000D /* Video Controller Origin Register */
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#define KA43_VDCSEL 0x2008000E /* Video Controller Select Register */
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#define KA43_INTREQ 0x2008000F /* Interrupt Request register */
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#define KA43_INTCLR 0x2008000F /* Interrupt Request clear register */
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#define KA43_DIAGDSP 0x20080010 /* Diagnostic display register */
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#define KA43_PARCTL 0x20080014 /* Parity Control Register */
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#define KA43_DIAGTME 0x2008001E /* diagnostic time register */
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#define KA43_PCTL_DPEN 0x00000001 /* DMA parity enable (bit 0) */
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#define KA43_PCTL_CPEN 0x00000002 /* CPU Parity enable (bit 1) */
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#define KA43_PCTL_DMA 0x01000000 /* LANCE DMA control (bit 24) */
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/*
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* "CH2" and "SESR" are two common names related to Secondary Cache
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*/
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#define KA43_SESR 0x21100000 /* same as KA43_CH2_CREG */
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#define KA43_SESR_CENB 0x00000001 /* Cache Enable */
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#define KA43_SESR_SERR 0x00000002
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#define KA43_SESR_LERR 0x00000004
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#define KA43_SESR_CERR 0x00000008
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#define KA43_SESR_DIRTY 0x00000010
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#define KA43_SESR_MISS 0x00000020
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#define KA43_SESR_DPE 0x00000040 /* Dal Parity Error */
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#define KA43_SESR_TPE 0x00000080 /* Tag Parity Error */
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#define KA43_SESR_WSB 0x00010000
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#define KA43_SESR_CIEA 0x7FFC0000
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#define KA43_SESR_BITS \
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"\020\010TPE\007DPE\006MISS\005DIRTY\004CERR\003LERR\002SERR\001ENABLE"
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/*
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* The following values refer to bits/bitfields within the 4 internal
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* registers controlling primary cache:
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* PR_PCTAG(124, tag-register) PR_PCIDX(125, index-register)
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* PR_PCERR(126, error-register) PR_PCSTS(127, status-register)
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*/
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#define KA43_PCTAG_TAG 0x1FFFF800 /* bits 11-29 */
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#define KA43_PCTAG_PARITY 0x40000000
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#define KA43_PCTAG_VALID 0x80000000
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#define KA43_PCIDX_INDEX 0x000007F8 /* 0x100 Q-word entries */
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#define KA43_PCERR_ADDR 0x3FFFFFFF
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#define KA43_PCS_FORCEHIT 0x00000001 /* Force hit */
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#define KA43_PCS_ENABLE 0x00000002 /* Enable primary cache */
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#define KA43_PCS_FLUSH 0x00000004 /* Flush cache */
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#define KA43_PCS_REFRESH 0x00000008 /* Enable refresh */
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#define KA43_PCS_HIT 0x00000010 /* Cache hit */
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#define KA43_PCS_INTERRUPT 0x00000020 /* Interrupt pending */
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#define KA43_PCS_TRAP2 0x00000040 /* Trap while trap */
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#define KA43_PCS_TRAP1 0x00000080 /* Micro trap/machine check */
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#define KA43_PCS_TPERR 0x00000100 /* Tag parity error */
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#define KA43_PCS_DPERR 0x00000200 /* Dal data parity error */
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#define KA43_PCS_PPERR 0x00000400 /* P data parity error */
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#define KA43_PCS_BUSERR 0x00000800 /* Bus error */
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#define KA43_PCS_BCHIT 0x00001000 /* B cache hit */
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#define KA43_PCSTS_BITS \
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"\020\015BCHIT\014BUSERR\013PPERR\012DPERR\011TPERR\010TRAP1" \
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"\007TRAP2\006INTR\005HIT\004REFRESH\003FLUSH\002ENABLE\001FORCEHIT"
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/*
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* Bits in PR_ACCS (Floating Point Accelerator Register)
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*/
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#define KA43_ACCS_VECTOR (1<<0) /* Vector Unit Present */
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#define KA43_ACCS_FCHIP (1<<1) /* FPU chip present */
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#define KA43_ACCS_WEP (1<<31) /* Write Even Parity */
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/*
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* Other fixed addresses which should be mapped
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*/
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#define KA43_CPU_BASE 0x20080000 /* so called "CPU registers" */
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#define KA43_CPU_END 0x200800FF
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#define KA43_CPU_SIZE 0x100
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#define KA43_NWA_BASE 0x20090000 /* Network Address ROM */
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#define KA43_NWA_END 0x2009007F
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#define KA43_NWA_SIZE 0x80
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#define KA43_SER_BASE 0x200A0000 /* Serial line controller */
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#define KA43_SER_END 0x200A000F
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#define KA43_SER_SIZE 0x10
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#define KA43_WAT_BASE 0x200B0000 /* TOY clock and NV-RAM */
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#define KA43_WAT_END 0x200B00FF
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#define KA43_WAT_SIZE 0x100
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#define KA43_SC1_BASE 0x200C0080 /* 1st SCSI Controller Chip */
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#define KA43_SC1_END 0x200C009F
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#define KA43_SC1_SIZE 0x20
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#define KA43_SC2_BASE 0x200C0180 /* 2nd SCSI Controller Chip */
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#define KA43_SC2_END 0x200C019F
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#define KA43_SC2_SIZE 0x20
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#define KA43_SCS_BASE 0x200C0000 /* area occupied by SCSI 1+2 */
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#define KA43_SCS_END 0x200C01FF
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#define KA43_SCS_SIZE 0x200
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#define KA43_LAN_BASE 0x200E0000 /* LANCE chip registers */
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#define KA43_LAN_END 0x200E0007
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#define KA43_LAN_SIZE 0x08
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#define KA43_CUR_BASE 0x200F0000 /* Monochrome video cursor chip */
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#define KA43_CUR_END 0x200F003C
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#define KA43_CUR_SIZE 0x40
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#define KA43_DMA_BASE 0x202D0000 /* 128KB Data Buffer */
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#define KA43_DMA_END 0x202EFFFF
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#define KA43_DMA_SIZE 0x20000
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#define KA43_VME_BASE 0x30000000
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#define KA43_VME_END 0x3003FFFF
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#define KA43_VME_SIZE 0x40000
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#define KA43_DIAGMEM 0x28000000 /* start of diagnostic memory */
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#define KA43_SC1_DADR 0x200C00A0 /* (1st SCSI) DMA address register */
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#define KA43_SC1_DCNT 0x200C00C0 /* (1st SCSI) DMA byte count reg. */
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#define KA43_SC1_DDIR 0x200C00C4 /* (1st SCSI) DMA transfer direction */
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#define KA43_SC2_DADR 0x200C01A0
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#define KA43_SC2_DCNT 0x200C01C0
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#define KA43_SC2_DDIR 0x200C01C4
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#define KA43_CUR_CMD 0x200F0000 /* Cursor Command Register */
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#define KA43_CUR_XPOS 0x200F0004 /* Cursor X position */
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#define KA43_CUR_YPOS 0x200F0008 /* Cursor Y position */
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#define KA43_CUR_XMIN1 0x200F000C /* Region 1 left edge */
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#define KA43_CUR_XMAX1 0x200F0010 /* Region 1 right edge */
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#define KA43_CUR_YMIN1 0x200F0014 /* Region 1 top edge */
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#define KA43_CUR_YMAX1 0x200F0018 /* Region 1 bottom edge */
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#define KA43_CUR_XMIN2 0x200F002C /* Region 2 left edge */
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#define KA43_CUR_XMAX2 0x200F0030 /* Region 2 right edge */
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#define KA43_CUR_YMIN2 0x200F0034 /* Region 2 top edge */
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#define KA43_CUR_YMAX2 0x200F0038 /* Region 2 bottom edge */
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/*
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* Clock-Chip data in NVRAM
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*/
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#define KA43_CPMBX 0x200B0038 /* Console Mailbox (1 byte) */
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#define KA43_CPFLG 0x200B003C /* Console Program Flags (1 byte) */
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#define KA43_LK201_ID 0x200B0040 /* Keyboard Variation (1 byte) */
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#define KA43_CONS_ID 0x200B0044 /* Console Device Type (1 byte) */
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#define KA43_SCR 0x200B0048 /* Console Scratch RAM */
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#define KA43_TEMP 0x200B0058 /* Used by System Firmware */
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#define KA43_BAT_CHK 0x200B0088 /* Battery Check Data */
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#define KA43_PASSWD 0x200B0098 /* ??? */
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#define KA43_BOOTFLG 0x200B00A8 /* Default Boot Flags (4 bytes) */
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#define KA43_SCRLEN 0x200B00B8 /* Number of pages of SCR (1 byte) */
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#define KA43_SCSIPORT 0x200B00BC /* Tape Controller Port Data */
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#define KA43_RESERVED 0x200B00C0 /* Reserved (16 bytes) */
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struct ka43_cpu {
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u_long hltcod; /* Halt Code Register */
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u_long pad2;
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u_long pad3;
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u_char intreg[4]; /* Four 1-byte registers */
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u_short diagdsp; /* Diagnostic display register */
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u_short pad4;
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u_long parctl; /* Parity Control Register */
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u_short pad5;
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u_short pad6;
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u_short pad7;
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u_short diagtme; /* Diagnostic time register */
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};
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struct ka43_clock {
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u_long :2; u_long sec :8; u_long :22;
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u_long :2; u_long secalrm :8; u_long :22;
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u_long :2; u_long min :8; u_long :22;
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u_long :2; u_long minalrm :8; u_long :22;
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u_long :2; u_long hr :8; u_long :22;
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u_long :2; u_long hralrm :8; u_long :22;
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u_long :2; u_long dayofwk :8; u_long :22;
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u_long :2; u_long day :8; u_long :22;
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u_long :2; u_long mon :8; u_long :22;
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u_long :2; u_long yr :8; u_long :22;
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u_long :2; u_long csr0 :8; u_long :22;
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u_long :2; u_long csr1 :8; u_long :22;
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u_long :2; u_long csr2 :8; u_long :22;
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u_long :2; u_long csr3 :8; u_long :22;
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u_long :2; u_long cpmbx :8; u_long :22;
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};
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int ka43_setup __P((struct uvax_calls *p, int flags));
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