77b78cdcff
- new code for Samsung S3C2440 SoC. - update for other S3C2xx0. This port was done by Paul Fleischer.
125 lines
3.9 KiB
C
125 lines
3.9 KiB
C
/*-
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Paul Fleischer <paul@xpg.dk>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/* This file implements a simple interface towards the S3C2440 DMA controller.
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At this point queueing of transfers is not supported. In other words, one
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has to be very careful that noone else is using a DMA channel when trying to use it.
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Only device<->memory transfers are supported at this time.
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Currently, the only usage of S3C2440 DMA is in the S3C2440 SD-Interface driver
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(s3c2440_sdi.c).
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*/
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#ifndef __S3C2440_DMA_H__
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#define __S3C2440_DMA_H__
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#include <sys/types.h>
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void s3c2440_dma_init(void);
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int s3c2440_dma_intr(void *arg);
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typedef enum {
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DMAC_BUS_TYPE_SYSTEM = 0,
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DMAC_BUS_TYPE_PERIPHERAL
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} dmac_bus_type_t;
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typedef enum {
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DMAC_SYNC_BUS_AUTO = 0,
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DMAC_SYNC_BUS_SYSTEM,
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DMAC_SYNC_BUS_PERIPHERAL
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} dmac_sync_bus_t;
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typedef enum {
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DMAC_XFER_WIDTH_8BIT = 0,
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DMAC_XFER_WIDTH_16BIT = 1,
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DMAC_XFER_WIDTH_32BIT = 2
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} dmac_xfer_width_t;
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typedef enum {
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DMAC_XFER_MODE_DEMAND = 0,
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DMAC_XFER_MODE_HANDSHAKE = 1
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} dmac_xfer_mode_t;
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typedef struct dmac_xfer_desc* dmac_xfer_desc_t;
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struct dmac_xfer_desc {
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dmac_bus_type_t xd_bus_type;
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bool xd_increment;
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u_int xd_nsegs;
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bus_dma_segment_t *xd_dma_segs;
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};
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typedef u_int dmac_peripheral_t;
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#define DMAC_PERIPH_NONE 0 /* Software triggered transfer */
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#define DMAC_PERIPH_XDREQ0 1
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#define DMAC_PERIPH_XDREQ1 2
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#define DMAC_PERIPH_UART0 3
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#define DMAC_PERIPH_UART1 4
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#define DMAC_PERIPH_UART2 5
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#define DMAC_PERIPH_I2SSDO 6
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#define DMAC_PERIPH_I2SSDI 7
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#define DMAC_PERIPH_SDI 8
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#define DMAC_PERIPH_SPI0 9
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#define DMAC_PERIPH_SPI1 10
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#define DMAC_PERIPH_PCMIN 11
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#define DMAC_PERIPH_PCMOUT 12
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#define DMAC_PERIPH_MICIN 13
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#define DMAC_PERIPH_MICOUT 14
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#define DMAC_PERIPH_TIMER 15
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#define DMAC_PERIPH_USBEP1 16
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#define DMAC_PERIPH_USBEP2 17
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#define DMAC_PERIPH_USBEP3 18
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#define DMAC_PERIPH_USBEP4 19
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#define DMAC_N_PERIPH 20
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typedef struct dmac_xfer* dmac_xfer_t;
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struct dmac_xfer {
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void (*dx_done)(dmac_xfer_t, void*);
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void *dx_cookie;
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dmac_peripheral_t dx_peripheral; /* Controls trigger mechanism
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and DMA channel to use */
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struct dmac_xfer_desc dx_desc[2];
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#define DMAC_DESC_SRC 0
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#define DMAC_DESC_DST 1
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dmac_sync_bus_t dx_sync_bus;
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dmac_xfer_width_t dx_xfer_width;
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dmac_xfer_mode_t dx_xfer_mode;
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};
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/* DMA API, inspired by pxa2x0_dmac.h */
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dmac_xfer_t s3c2440_dmac_allocate_xfer(int);
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void s3c2440_dmac_free_xfer(dmac_xfer_t);
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int s3c2440_dmac_start_xfer(dmac_xfer_t);
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void s3c2440_dmac_abort_xfer(dmac_xfer_t);
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int s3c2440_dmac_wait_xfer(dmac_xfer_t, int);
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#endif
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