489 lines
11 KiB
C
489 lines
11 KiB
C
/* $NetBSD: pcs_bus_io_common.c,v 1.6 1996/07/09 00:54:57 cgd Exp $ */
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/*
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* Copyright (c) 1995, 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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/*
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* Common PCI Chipset "bus I/O" functions, for chipsets which have to
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* deal with only a single PCI interface chip in a machine.
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*
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* uses:
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* CHIP name of the 'chip' it's being compiled for.
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* CHIP_IO_BASE Sparse I/O space base to use.
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*/
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#define __C(A,B) __CONCAT(A,B)
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#define __S(S) __STRING(S)
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int __C(CHIP,_io_map) __P((void *, bus_io_addr_t, bus_io_size_t,
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bus_io_handle_t *));
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void __C(CHIP,_io_unmap) __P((void *, bus_io_handle_t,
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bus_io_size_t));
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int __C(CHIP,_io_subregion) __P((void *, bus_io_handle_t,
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bus_io_size_t, bus_io_size_t, bus_io_handle_t *));
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u_int8_t __C(CHIP,_io_read_1) __P((void *, bus_io_handle_t,
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bus_io_size_t));
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u_int16_t __C(CHIP,_io_read_2) __P((void *, bus_io_handle_t,
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bus_io_size_t));
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u_int32_t __C(CHIP,_io_read_4) __P((void *, bus_io_handle_t,
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bus_io_size_t));
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u_int64_t __C(CHIP,_io_read_8) __P((void *, bus_io_handle_t,
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bus_io_size_t));
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void __C(CHIP,_io_read_multi_1) __P((void *, bus_io_handle_t,
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bus_io_size_t, u_int8_t *, bus_io_size_t));
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void __C(CHIP,_io_read_multi_2) __P((void *, bus_io_handle_t,
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bus_io_size_t, u_int16_t *, bus_io_size_t));
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void __C(CHIP,_io_read_multi_4) __P((void *, bus_io_handle_t,
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bus_io_size_t, u_int32_t *, bus_io_size_t));
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void __C(CHIP,_io_read_multi_8) __P((void *, bus_io_handle_t,
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bus_io_size_t, u_int64_t *, bus_io_size_t));
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void __C(CHIP,_io_write_1) __P((void *, bus_io_handle_t,
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bus_io_size_t, u_int8_t));
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void __C(CHIP,_io_write_2) __P((void *, bus_io_handle_t,
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bus_io_size_t, u_int16_t));
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void __C(CHIP,_io_write_4) __P((void *, bus_io_handle_t,
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bus_io_size_t, u_int32_t));
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void __C(CHIP,_io_write_8) __P((void *, bus_io_handle_t,
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bus_io_size_t, u_int64_t));
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void __C(CHIP,_io_write_multi_1) __P((void *, bus_io_handle_t,
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bus_io_size_t, const u_int8_t *, bus_io_size_t));
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void __C(CHIP,_io_write_multi_2) __P((void *, bus_io_handle_t,
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bus_io_size_t, const u_int16_t *, bus_io_size_t));
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void __C(CHIP,_io_write_multi_4) __P((void *, bus_io_handle_t,
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bus_io_size_t, const u_int32_t *, bus_io_size_t));
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void __C(CHIP,_io_write_multi_8) __P((void *, bus_io_handle_t,
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bus_io_size_t, const u_int64_t *, bus_io_size_t));
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void
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__C(CHIP,_bus_io_init)(bc, iov)
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bus_chipset_tag_t bc;
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void *iov;
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{
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bc->bc_i_v = iov;
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bc->bc_i_map = __C(CHIP,_io_map);
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bc->bc_i_unmap = __C(CHIP,_io_unmap);
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bc->bc_i_subregion = __C(CHIP,_io_subregion);
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bc->bc_ir1 = __C(CHIP,_io_read_1);
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bc->bc_ir2 = __C(CHIP,_io_read_2);
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bc->bc_ir4 = __C(CHIP,_io_read_4);
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bc->bc_ir8 = __C(CHIP,_io_read_8);
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bc->bc_irm1 = __C(CHIP,_io_read_multi_1);
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bc->bc_irm2 = __C(CHIP,_io_read_multi_2);
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bc->bc_irm4 = __C(CHIP,_io_read_multi_4);
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bc->bc_irm8 = __C(CHIP,_io_read_multi_8);
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bc->bc_iw1 = __C(CHIP,_io_write_1);
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bc->bc_iw2 = __C(CHIP,_io_write_2);
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bc->bc_iw4 = __C(CHIP,_io_write_4);
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bc->bc_iw8 = __C(CHIP,_io_write_8);
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bc->bc_iwm1 = __C(CHIP,_io_write_multi_1);
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bc->bc_iwm2 = __C(CHIP,_io_write_multi_2);
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bc->bc_iwm4 = __C(CHIP,_io_write_multi_4);
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bc->bc_iwm8 = __C(CHIP,_io_write_multi_8);
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}
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int
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__C(CHIP,_io_map)(v, ioaddr, iosize, iohp)
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void *v;
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bus_io_addr_t ioaddr;
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bus_io_size_t iosize;
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bus_io_handle_t *iohp;
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{
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#ifdef CHIP_IO_W1_START
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if (ioaddr >= CHIP_IO_W1_START(v) &&
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ioaddr <= CHIP_IO_W1_END(v)) {
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*iohp = (ALPHA_PHYS_TO_K0SEG(CHIP_IO_W1_BASE(v)) >> 5) +
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(ioaddr & CHIP_IO_W1_MASK(v));
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} else
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#endif
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#ifdef CHIP_IO_W2_START
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if (ioaddr >= CHIP_IO_W2_START(v) &&
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ioaddr <= CHIP_IO_W2_END(v)) {
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*iohp = (ALPHA_PHYS_TO_K0SEG(CHIP_IO_W2_BASE(v)) >> 5) +
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(ioaddr & CHIP_IO_W2_MASK(v));
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} else
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#endif
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{
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printf("\n");
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#ifdef CHIP_IO_W1_START
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printf("%s: window[1]=0x%lx-0x%lx\n",
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__S(__C(CHIP,_io_map)), CHIP_IO_W1_START(v),
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CHIP_IO_W1_END(v)-1);
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#endif
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#ifdef CHIP_IO_W2_START
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printf("%s: window[2]=0x%lx-0x%lx\n",
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__S(__C(CHIP,_io_map)), CHIP_IO_W2_START(v),
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CHIP_IO_W2_END(v)-1);
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#endif
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panic("%s: don't know how to map %lx non-cacheable\n",
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__S(__C(CHIP,_io_map)), ioaddr);
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}
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return (0);
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}
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void
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__C(CHIP,_io_unmap)(v, ioh, iosize)
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void *v;
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bus_io_handle_t ioh;
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bus_io_size_t iosize;
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{
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/* XXX nothing to do. */
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}
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int
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__C(CHIP,_io_subregion)(v, ioh, offset, size, nioh)
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void *v;
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bus_io_handle_t ioh, *nioh;
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bus_io_size_t offset, size;
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{
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*nioh = ioh + offset;
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return (0);
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}
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u_int8_t
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__C(CHIP,_io_read_1)(v, ioh, off)
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void *v;
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bus_io_handle_t ioh;
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bus_io_size_t off;
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{
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register bus_io_handle_t tmpioh;
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register u_int32_t *port, val;
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register u_int8_t rval;
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register int offset;
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alpha_mb();
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tmpioh = ioh + off;
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offset = tmpioh & 3;
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port = (u_int32_t *)((tmpioh << 5) | (0 << 3));
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val = *port;
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rval = ((val) >> (8 * offset)) & 0xff;
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return rval;
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}
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u_int16_t
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__C(CHIP,_io_read_2)(v, ioh, off)
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void *v;
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bus_io_handle_t ioh;
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bus_io_size_t off;
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{
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register bus_io_handle_t tmpioh;
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register u_int32_t *port, val;
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register u_int16_t rval;
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register int offset;
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alpha_mb();
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tmpioh = ioh + off;
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offset = tmpioh & 3;
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port = (u_int32_t *)((tmpioh << 5) | (1 << 3));
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val = *port;
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rval = ((val) >> (8 * offset)) & 0xffff;
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return rval;
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}
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u_int32_t
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__C(CHIP,_io_read_4)(v, ioh, off)
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void *v;
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bus_io_handle_t ioh;
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bus_io_size_t off;
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{
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register bus_io_handle_t tmpioh;
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register u_int32_t *port, val;
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register u_int32_t rval;
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register int offset;
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alpha_mb();
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tmpioh = ioh + off;
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offset = tmpioh & 3;
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port = (u_int32_t *)((tmpioh << 5) | (3 << 3));
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val = *port;
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#if 0
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rval = ((val) >> (8 * offset)) & 0xffffffff;
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#else
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rval = val;
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#endif
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return rval;
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}
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u_int64_t
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__C(CHIP,_io_read_8)(v, ioh, off)
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void *v;
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bus_io_handle_t ioh;
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bus_io_size_t off;
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{
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/* XXX XXX XXX */
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panic("%s not implemented\n", __S(__C(CHIP,_io_read_8)));
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}
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void
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__C(CHIP,_io_read_multi_1)(v, ioh, off, addr, count)
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void *v;
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bus_io_handle_t ioh;
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bus_io_size_t off, count;
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u_int8_t *addr;
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{
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register bus_io_handle_t tmpioh;
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register u_int32_t *port, val;
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register int offset;
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alpha_mb();
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while (count--) {
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tmpioh = ioh + off;
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offset = tmpioh & 3;
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port = (u_int32_t *)((tmpioh << 5) | (0 << 3));
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val = *port;
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*addr++ = ((val) >> (8 * offset)) & 0xff;
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off++;
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}
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}
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void
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__C(CHIP,_io_read_multi_2)(v, ioh, off, addr, count)
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void *v;
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bus_io_handle_t ioh;
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bus_io_size_t off, count;
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u_int16_t *addr;
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{
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register bus_io_handle_t tmpioh;
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register u_int32_t *port, val;
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register int offset;
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alpha_mb();
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while (count--) {
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tmpioh = ioh + off;
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offset = tmpioh & 3;
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port = (u_int32_t *)((tmpioh << 5) | (1 << 3));
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val = *port;
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*addr++ = ((val) >> (8 * offset)) & 0xffff;
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off++;
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}
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}
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void
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__C(CHIP,_io_read_multi_4)(v, ioh, off, addr, count)
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void *v;
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bus_io_handle_t ioh;
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bus_io_size_t off, count;
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u_int32_t *addr;
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{
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register bus_io_handle_t tmpioh;
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register u_int32_t *port, val;
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register int offset;
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alpha_mb();
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while (count--) {
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tmpioh = ioh + off;
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offset = tmpioh & 3;
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port = (u_int32_t *)((tmpioh << 5) | (3 << 3));
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val = *port;
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#if 0
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*addr++ = ((val) >> (8 * offset)) & 0xffffffff;
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#else
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*addr++ = val;
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#endif
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off++;
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}
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}
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void
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__C(CHIP,_io_read_multi_8)(v, ioh, off, addr, count)
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void *v;
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bus_io_handle_t ioh;
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bus_io_size_t off, count;
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u_int64_t *addr;
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{
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/* XXX XXX XXX */
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panic("%s not implemented\n", __S(__C(CHIP,_io_read_multi_8)));
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}
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void
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__C(CHIP,_io_write_1)(v, ioh, off, val)
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void *v;
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bus_io_handle_t ioh;
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bus_io_size_t off;
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u_int8_t val;
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{
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register bus_io_handle_t tmpioh;
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register u_int32_t *port, nval;
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register int offset;
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tmpioh = ioh + off;
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offset = tmpioh & 3;
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nval = val << (8 * offset);
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port = (u_int32_t *)((tmpioh << 5) | (0 << 3));
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*port = nval;
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alpha_mb();
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}
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void
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__C(CHIP,_io_write_2)(v, ioh, off, val)
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void *v;
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bus_io_handle_t ioh;
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bus_io_size_t off;
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u_int16_t val;
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{
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register bus_io_handle_t tmpioh;
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register u_int32_t *port, nval;
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register int offset;
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tmpioh = ioh + off;
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offset = tmpioh & 3;
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nval = val << (8 * offset);
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port = (u_int32_t *)((tmpioh << 5) | (1 << 3));
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*port = nval;
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alpha_mb();
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}
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void
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__C(CHIP,_io_write_4)(v, ioh, off, val)
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void *v;
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bus_io_handle_t ioh;
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bus_io_size_t off;
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u_int32_t val;
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{
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register bus_io_handle_t tmpioh;
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register u_int32_t *port, nval;
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register int offset;
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tmpioh = ioh + off;
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offset = tmpioh & 3;
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nval = val /*<< (8 * offset)*/;
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port = (u_int32_t *)((tmpioh << 5) | (3 << 3));
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*port = nval;
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alpha_mb();
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}
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void
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__C(CHIP,_io_write_8)(v, ioh, off, val)
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void *v;
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bus_io_handle_t ioh;
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bus_io_size_t off;
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u_int64_t val;
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{
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/* XXX XXX XXX */
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panic("%s not implemented\n", __S(__C(CHIP,_io_write_8)));
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alpha_mb();
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}
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void
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__C(CHIP,_io_write_multi_1)(v, ioh, off, addr, count)
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void *v;
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bus_io_handle_t ioh;
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bus_io_size_t off, count;
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const u_int8_t *addr;
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{
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register bus_io_handle_t tmpioh;
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register u_int32_t *port, nval;
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register int offset;
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while (count--) {
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tmpioh = ioh + off;
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offset = tmpioh & 3;
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nval = (*addr++) << (8 * offset);
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port = (u_int32_t *)((tmpioh << 5) | (0 << 3));
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*port = nval;
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off++;
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}
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alpha_mb();
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}
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void
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__C(CHIP,_io_write_multi_2)(v, ioh, off, addr, count)
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void *v;
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bus_io_handle_t ioh;
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bus_io_size_t off, count;
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const u_int16_t *addr;
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{
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register bus_io_handle_t tmpioh;
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register u_int32_t *port, nval;
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register int offset;
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while (count--) {
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tmpioh = ioh + off;
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offset = tmpioh & 3;
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nval = (*addr++) << (8 * offset);
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port = (u_int32_t *)((tmpioh << 5) | (1 << 3));
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*port = nval;
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off++;
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}
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alpha_mb();
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}
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void
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__C(CHIP,_io_write_multi_4)(v, ioh, off, addr, count)
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void *v;
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bus_io_handle_t ioh;
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bus_io_size_t off, count;
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const u_int32_t *addr;
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{
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register bus_io_handle_t tmpioh;
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register u_int32_t *port, nval;
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register int offset;
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while (count--) {
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tmpioh = ioh + off;
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offset = tmpioh & 3;
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nval = (*addr++) /*<< (8 * offset)*/;
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port = (u_int32_t *)((tmpioh << 5) | (3 << 3));
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*port = nval;
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off++;
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}
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alpha_mb();
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}
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void
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__C(CHIP,_io_write_multi_8)(v, ioh, off, addr, count)
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void *v;
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bus_io_handle_t ioh;
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|
bus_io_size_t off, count;
|
|
const u_int64_t *addr;
|
|
{
|
|
|
|
/* XXX XXX XXX */
|
|
panic("%s not implemented\n", __S(__C(CHIP,_io_write_multi_8)));
|
|
}
|