497d6762cf
common across many of the 4xx parts. Leaves ibm405gp.h with device address information specific to the 405GP CPU. Now allows opb.c to support multiple 4xx CPU types.
106 lines
3.7 KiB
C
106 lines
3.7 KiB
C
/* $NetBSD: pcicreg.h,v 1.1 2002/08/13 04:57:49 simonb Exp $ */
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/*
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* Copyright 2001 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Simon Burge and Eduardo Horvath for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _IBM4XX_PCICREG_H_
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#define _IBM4XX_PCICREG_H_
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/* PCI Configuaration Registers */
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#define PCIC_CFGADDR 0x00
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#define PCIC_CFGDATA 0x04
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#define PCIC_VENDID 0x00
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#define PCIC_DEVID 0x02
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#define PCIC_CMD 0x04
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#define PCIC_STATUS 0x06
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#define PCIC_REVID 0x08
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#define PCIC_CLS 0x09
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#define PCIC_CACHELS 0x0c
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#define PCIC_LATTIM 0x0d
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#define PCIC_HDTYPE 0x0e
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#define PCIC_BIST 0x0f
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#define PCIC_BAR0 0x10
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#define PCIC_BAR1 0x14 /* PCI name */
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#define PCIC_PTM1BAR PCIC_BAR1 /* 405GP name */
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#define PCIC_BAR2 0x18 /* PCI name */
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#define PCIC_PTM2BAR PCIC_BAR2 /* 405GP name */
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#define PCIC_BAR3 0x1C
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#define PCIC_BAR4 0x20
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#define PCIC_BAR5 0x24
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#define PCIC_SBSYSVID 0x2c
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#define PCIC_SBSYSID 0x2e
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#define PCIC_CAP 0x34
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#define PCIC_INTLN 0x3c
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#define PCIC_INTPN 0x3d
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#define PCIC_MINGNT 0x3e
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#define PCIC_MAXLTNCY 0x3f
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#define PCIC_ICS 0x44 /* 405GP specific parameters */
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#define PCIC_ERREN 0x48
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#define PCIC_ERRSTS 0x49
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#define PCIC_BRDGOPT1 0x4a
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#define PCIC_PLBBESR0 0x4c
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#define PCIC_PLBBESR1 0x50
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#define PCIC_PLBBEAR 0x54
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#define PCIC_CAPID 0x58
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#define PCIC_NEXTIPTR 0x59
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#define PCIC_PMC 0x5a
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#define PCIC_PMCSR 0x5c
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#define PCIC_PMCSRBSE 0x5e
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#define PCIC_DATA 0x5f
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#define PCIC_BRDGOPT2 0x60
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#define PCIC_PMSCRR 0x64
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/* PCI Bridge Local Configuation Registers (0xef400000 0xef40003f - 64 bytes) */
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#define PCIL_PMM0LA 0x00 /* PCI Master Map 0: Local Address */
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#define PCIL_PMM0MA 0x04 /* Mask/Attribute */
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#define PCIL_PMM0PCILA 0x08 /* PCI Low Address */
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#define PCIL_PMM0PCIHA 0x0c /* PCI High Address */
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#define PCIL_PMM1LA 0x10
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#define PCIL_PMM1MA 0x14
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#define PCIL_PMM1PCILA 0x18
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#define PCIL_PMM1PCIHA 0x1c
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#define PCIL_PMM2LA 0x20
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#define PCIL_PMM2MA 0x24
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#define PCIL_PMM2PCILA 0x28
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#define PCIL_PMM2PCIHA 0x2c
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#define PCIL_PTM1MS 0x30
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#define PCIL_PTM1LA 0x34
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#define PCIL_PTM2MS 0x38
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#define PCIL_PTM2LA 0x3c
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#endif /* _IBM4XX_PCICREG_H_ */
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