147 lines
6.0 KiB
C
147 lines
6.0 KiB
C
/* $NetBSD: elan520reg.h,v 1.1 2002/08/12 01:03:14 thorpej Exp $ */
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/*-
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* Copyright (c) 2002 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Register definitions for the AMD Elan SC520 System Controller.
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*/
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#ifndef _I386_PCI_ELAN520REG_H_
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#define _I386_PCI_ELAN520REG_H_
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#define MMCR_BASE_ADDR 0xfffef000
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/*
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* Am5x86 CPU Registers.
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*/
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#define MMCR_REVID 0x0000
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#define MMCR_CPUCTL 0x0002
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#define REVID_PRODID 0xff00 /* product ID */
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#define REVID_PRODID_SHIFT 8
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#define REVID_MAJSTEP 0x00f0 /* stepping major */
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#define REVID_MAJSTEP_SHIFT 4
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#define REVID_MINSTEP 0x000f /* stepping minor */
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#define PRODID_ELAN_SC520 0x00 /* Elan SC520 */
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#define CPUCTL_CPU_CLK_SPD_MASK 0x03 /* CPU clock speed */
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#define CPUCTL_CACHE_WR_MODE 0x10 /* cache mode (0 = wb, 1 = wt) */
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/*
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* General Purpose Bus Registers
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*/
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#define MMCR_GPECHO 0x0c00 /* GP echo mode */
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#define MMCR_GPCSDW 0x0c01 /* GP chip sel data width */
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#define MMCR_CPCSQUAL 0x0c02 /* GP chip sel qualification */
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#define MMCR_GPCSRT 0x0c08 /* GP chip sel recovery time */
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#define MMCR_GPCSPW 0x0c09 /* GP chip sel pulse width */
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#define MMCR_GPCSOFF 0x0c0a /* GP chip sel offset */
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#define MMCR_GPRDW 0x0c0b /* GP read pulse width */
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#define MMCR_GPRDOFF 0x0c0c /* GP read offset */
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#define MMCR_GPWRW 0x0c0d /* GP write pulse width */
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#define MMCR_GPWROFF 0x0c0e /* GP write offset */
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#define MMCR_GPALEW 0x0c0f /* GPALE pulse width */
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#define MMCR_GPALEOFF 0x0c10 /* GPALE offset */
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#define GPECHO_GP_ECHO_ENB 0x01 /* GP bus echo mode enable */
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/*
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* Programmable Input/Output Registers
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*/
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#define MMCR_PIOPFS15_0 0x0c20 /* PIO15-PIO0 pin func sel */
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#define MMCR_PIOPFS31_16 0x0c22 /* PIO31-PIO16 pin func sel */
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#define MMCR_CSPFS 0x0c24 /* chip sel pin func sel */
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#define MMCR_CLKSEL 0x0c26 /* clock select */
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#define MMCR_DSCTL 0x0c28 /* drive strength control */
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#define MMCR_PIODIR15_0 0x0c2a /* PIO15-PIO0 direction */
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#define MMCR_PIODIR31_16 0x0c2c /* PIO31-PIO16 direction */
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#define MMCR_PIODATA15_0 0x0c30 /* PIO15-PIO0 data */
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#define MMCR_PIODATA31_16 0x0c32 /* PIO31-PIO16 data */
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#define MMCR_PIOSET15_0 0x0c34 /* PIO15-PIO0 set */
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#define MMCR_PIOSET31_16 0x0c36 /* PIO31-PIO16 set */
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#define MMCR_PIOCLR15_0 0x0c38 /* PIO15-PIO0 clear */
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#define MMCR_PIOCLR31_16 0x0c3a /* PIO31-PIO16 clear */
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/*
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* Watchdog Timer Registers.
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*/
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#define MMCR_WDTMRCTL 0x0cb0 /* watchdog timer control */
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#define MMCR_WDTMRCNTL 0x0cb2 /* watchdog timer count low */
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#define MMCR_WDTMRCNTH 0x0cb4 /* watchdog timer count high */
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#define WDTMRCTL_EXP_SEL_MASK 0x00ff /* exponent select */
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#define WDTMRCTL_EXP_SEL14 0x0001 /* 496us/492us */
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#define WDTMRCTL_EXP_SEL24 0x0002 /* 508ms/503ms */
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#define WDTMRCTL_EXP_SEL25 0x0004 /* 1.02s/1.01s */
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#define WDTMRCTL_EXP_SEL26 0x0008 /* 2.03s/2.01s */
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#define WDTMRCTL_EXP_SEL27 0x0010 /* 4.07s/4.03s */
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#define WDTMRCTL_EXP_SEL28 0x0020 /* 8.13s/8.05s */
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#define WDTMRCTL_EXP_SEL29 0x0040 /* 16.27s/16.11s */
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#define WDTMRCTL_EXP_SEL30 0x0080 /* 32.54s/32.21s */
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#define WDTMRCTL_IRQ_FLG 0x1000 /* interrupt request */
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#define WDTMRCTL_WRST_ENB 0x4000 /* watchdog timer reset enable */
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#define WDTMRCTL_ENB 0x8000 /* watchdog timer enable */
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#define WDTMRCTL_UNLOCK1 0x3333
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#define WDTMRCTL_UNLOCK2 0xcccc
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#define WDTMRCTL_RESET1 0xaaaa
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#define WDTMRCTL_RESET2 0x5555
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/*
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* Reset Generation Registers.
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*/
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#define MMCR_SYSINFO 0x0d70 /* system board information */
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#define MMCR_RESCFG 0x0d72 /* reset configuration */
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#define MMCR_RESSTA 0x0d74 /* reset status */
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#define RESCFG_SYS_RST 0x01 /* software system reset */
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#define RESCFG_GP_RST 0x02 /* assert GP bus reset */
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#define RESCFG_PRG_RST_ENB 0x04 /* programmable reset enable */
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#define RESCFG_ICE_ON_RST 0x08 /* enter AMDebug(tm) on reset */
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#define RESSTA_PWRGOOD_DET 0x01 /* POWERGOOD reset detect */
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#define RESSTA_PRGRST_DET 0x02 /* programmable reset detect */
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#define RESSTA_SD_RST_DET 0x04 /* CPU shutdown reset detect */
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#define RESSTA_WDT_RST_DET 0x08 /* watchdog timer reset detect */
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#define RESSTA_ICE_SRST_DET 0x10 /* AMDebug(tm) soft reset detect */
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#define RESSTA_ICE_HRST_DET 0x20 /* AMDebug(tm) soft reset detect */
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#define RESSTA_SCP_RST 0x40 /* SCP reset detect */
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#endif /* _I386_PCI_ELAN520REG_H_ */
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