289 lines
8.4 KiB
C
289 lines
8.4 KiB
C
/* $NetBSD: elan520.c,v 1.8 2003/12/04 13:05:16 keihan Exp $ */
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/*-
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* Copyright (c) 2002 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Device driver for the AMD Elan SC520 System Controller. This attaches
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* where the "pchb" driver might normally attach, and provides support for
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* extra features on the SC520, such as the watchdog timer and GPIO.
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*
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* Information about the GP bus echo bug work-around is from code posted
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* to the "soekris-tech" mailing list by Jasper Wallace.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: elan520.c,v 1.8 2003/12/04 13:05:16 keihan Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/wdog.h>
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#include <uvm/uvm_extern.h>
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#include <machine/bus.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <arch/i386/pci/elan520reg.h>
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#include <dev/sysmon/sysmonvar.h>
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struct elansc_softc {
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struct device sc_dev;
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bus_space_tag_t sc_memt;
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bus_space_handle_t sc_memh;
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int sc_echobug;
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struct sysmon_wdog sc_smw;
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};
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static void
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elansc_wdogctl_write(struct elansc_softc *sc, uint16_t val)
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{
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int s;
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uint8_t echo_mode = 0; /* XXX: gcc */
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s = splhigh();
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/* Switch off GP bus echo mode if we need to. */
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if (sc->sc_echobug) {
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echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh,
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MMCR_GPECHO);
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bus_space_write_1(sc->sc_memt, sc->sc_memh,
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MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB);
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}
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/* Unlock the register. */
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bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL,
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WDTMRCTL_UNLOCK1);
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bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL,
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WDTMRCTL_UNLOCK2);
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/* Write the value. */
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bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, val);
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/* Switch GP bus echo mode back. */
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if (sc->sc_echobug)
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bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO,
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echo_mode);
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splx(s);
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}
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static void
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elansc_wdogctl_reset(struct elansc_softc *sc)
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{
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int s;
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uint8_t echo_mode = 0/* XXX: gcc */;
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s = splhigh();
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/* Switch off GP bus echo mode if we need to. */
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if (sc->sc_echobug) {
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echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh,
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MMCR_GPECHO);
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bus_space_write_1(sc->sc_memt, sc->sc_memh,
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MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB);
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}
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/* Reset the watchdog. */
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bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL,
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WDTMRCTL_RESET1);
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bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL,
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WDTMRCTL_RESET2);
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/* Switch GP bus echo mode back. */
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if (sc->sc_echobug)
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bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO,
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echo_mode);
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splx(s);
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}
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static const struct {
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int period; /* whole seconds */
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uint16_t exp; /* exponent select */
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} elansc_wdog_periods[] = {
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{ 1, WDTMRCTL_EXP_SEL25 },
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{ 2, WDTMRCTL_EXP_SEL26 },
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{ 4, WDTMRCTL_EXP_SEL27 },
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{ 8, WDTMRCTL_EXP_SEL28 },
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{ 16, WDTMRCTL_EXP_SEL29 },
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{ 32, WDTMRCTL_EXP_SEL30 },
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{ 0, 0 },
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};
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static int
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elansc_wdog_setmode(struct sysmon_wdog *smw)
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{
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struct elansc_softc *sc = smw->smw_cookie;
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int i;
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uint16_t exp_sel = 0; /* XXX: gcc */
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if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) {
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elansc_wdogctl_write(sc,
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WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30);
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} else {
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if (smw->smw_period == WDOG_PERIOD_DEFAULT) {
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smw->smw_period = 32;
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exp_sel = WDTMRCTL_EXP_SEL30;
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} else {
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for (i = 0; elansc_wdog_periods[i].period != 0; i++) {
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if (elansc_wdog_periods[i].period ==
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smw->smw_period) {
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exp_sel = elansc_wdog_periods[i].exp;
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break;
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}
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}
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if (elansc_wdog_periods[i].period == 0)
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return (EINVAL);
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}
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elansc_wdogctl_write(sc, WDTMRCTL_ENB |
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WDTMRCTL_WRST_ENB | exp_sel);
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elansc_wdogctl_reset(sc);
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}
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return (0);
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}
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static int
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elansc_wdog_tickle(struct sysmon_wdog *smw)
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{
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struct elansc_softc *sc = smw->smw_cookie;
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elansc_wdogctl_reset(sc);
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return (0);
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}
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static int
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elansc_match(struct device *parent, struct cfdata *match, void *aux)
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{
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struct pci_attach_args *pa = aux;
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD &&
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PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_SC520_SC)
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return (10); /* beat pchb */
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return (0);
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}
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static const char *elansc_speeds[] = {
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"(reserved 00)",
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"100MHz",
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"133MHz",
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"(reserved 11)",
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};
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static void
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elansc_attach(struct device *parent, struct device *self, void *aux)
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{
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struct elansc_softc *sc = (void *) self;
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struct pci_attach_args *pa = aux;
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uint16_t rev;
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uint8_t ressta, cpuctl;
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printf(": AMD Elan SC520 System Controller\n");
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sc->sc_memt = pa->pa_memt;
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if (bus_space_map(sc->sc_memt, MMCR_BASE_ADDR, PAGE_SIZE, 0,
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&sc->sc_memh) != 0) {
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printf("%s: unable to map registers\n", sc->sc_dev.dv_xname);
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return;
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}
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rev = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_REVID);
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cpuctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_CPUCTL);
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printf("%s: product %d stepping %d.%d, CPU clock %s\n",
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sc->sc_dev.dv_xname,
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(rev & REVID_PRODID) >> REVID_PRODID_SHIFT,
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(rev & REVID_MAJSTEP) >> REVID_MAJSTEP_SHIFT,
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(rev & REVID_MINSTEP),
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elansc_speeds[cpuctl & CPUCTL_CPU_CLK_SPD_MASK]);
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/*
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* SC520 rev A1 has a bug that affects the watchdog timer. If
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* the GP bus echo mode is enabled, writing to the watchdog control
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* register is blocked.
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*
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* The BIOS in some systems (e.g. the Soekris net4501) enables
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* GP bus echo for various reasons, so we need to switch it off
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* when we talk to the watchdog timer.
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*
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* XXX The step 1.1 (B1?) in my Soekris net4501 also has this
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* XXX problem, so we'll just enable it for all Elan SC520s
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* XXX for now. --thorpej@NetBSD.org
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*/
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if (1 || rev == ((PRODID_ELAN_SC520 << REVID_PRODID_SHIFT) |
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(0 << REVID_MAJSTEP_SHIFT) | (1)))
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sc->sc_echobug = 1;
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/*
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* Determine cause of the last reset, and issue a warning if it
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* was due to watchdog expiry.
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*/
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ressta = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA);
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if (ressta & RESSTA_WDT_RST_DET)
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printf("%s: WARNING: LAST RESET DUE TO WATCHDOG EXPIRATION!\n",
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sc->sc_dev.dv_xname);
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bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA, ressta);
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/*
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* Hook up the watchdog timer.
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*/
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sc->sc_smw.smw_name = sc->sc_dev.dv_xname;
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sc->sc_smw.smw_cookie = sc;
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sc->sc_smw.smw_setmode = elansc_wdog_setmode;
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sc->sc_smw.smw_tickle = elansc_wdog_tickle;
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sc->sc_smw.smw_period = 32; /* actually 32.54 */
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if (sysmon_wdog_register(&sc->sc_smw) != 0)
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printf("%s: unable to register watchdog with sysmon\n",
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sc->sc_dev.dv_xname);
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/* Set up the watchdog registers with some defaults. */
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elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30);
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/* ...and clear it. */
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elansc_wdogctl_reset(sc);
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}
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CFATTACH_DECL(elansc, sizeof(struct elansc_softc),
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elansc_match, elansc_attach, NULL, NULL);
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