223 lines
6.2 KiB
ArmAsm
223 lines
6.2 KiB
ArmAsm
/* $NetBSD: cpufunc_asm_armv5.S,v 1.2 2005/12/11 12:16:41 christos Exp $ */
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/*
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* Copyright (c) 2002, 2005 ARM Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* ARMv5 assembly functions for manipulating caches.
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* These routines can be used by any core that supports the set/index
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* operations.
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*/
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#include <machine/cpu.h>
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#include <machine/asm.h>
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/*
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* Cache operations. For the entire cache we use the set/index
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* operations.
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*/
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s_max .req r0
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i_max .req r1
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s_inc .req r2
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i_inc .req r3
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ENTRY_NP(armv5_icache_sync_range)
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ldr ip, .Larmv5_line_size
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cmp r1, #0x4000
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bcs .Larmv5_icache_sync_all
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ldr ip, [ip]
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sub r1, r1, #1 /* Don't overrun */
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sub r3, ip, #1
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and r2, r0, r3
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add r1, r1, r2
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bic r0, r0, r3
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1:
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mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
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mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
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add r0, r0, ip
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subs r1, r1, ip
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bpl 1b
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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RET
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ENTRY_NP(armv5_icache_sync_all)
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.Larmv5_icache_sync_all:
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/*
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* We assume that the code here can never be out of sync with the
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* dcache, so that we can safely flush the Icache and fall through
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* into the Dcache cleaning code.
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*/
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mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
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/* Fall through to clean Dcache. */
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.Larmv5_dcache_wb:
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ldr ip, .Larmv5_cache_data
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ldmia ip, {s_max, i_max, s_inc, i_inc}
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1:
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orr ip, s_max, i_max
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2:
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mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
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sub ip, ip, i_inc
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tst ip, i_max /* Index 0 is last one */
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bne 2b /* Next index */
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mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
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subs s_max, s_max, s_inc
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bpl 1b /* Next set */
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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RET
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.Larmv5_line_size:
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.word _C_LABEL(arm_pdcache_line_size)
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ENTRY(armv5_dcache_wb_range)
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ldr ip, .Larmv5_line_size
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cmp r1, #0x4000
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bcs .Larmv5_dcache_wb
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ldr ip, [ip]
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sub r1, r1, #1 /* Don't overrun */
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sub r3, ip, #1
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and r2, r0, r3
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add r1, r1, r2
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bic r0, r0, r3
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1:
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mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
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add r0, r0, ip
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subs r1, r1, ip
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bpl 1b
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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RET
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ENTRY(armv5_dcache_wbinv_range)
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ldr ip, .Larmv5_line_size
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cmp r1, #0x4000
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bcs .Larmv5_dcache_wbinv_all
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ldr ip, [ip]
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sub r1, r1, #1 /* Don't overrun */
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sub r3, ip, #1
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and r2, r0, r3
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add r1, r1, r2
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bic r0, r0, r3
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1:
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mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
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add r0, r0, ip
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subs r1, r1, ip
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bpl 1b
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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RET
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/*
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* Note, we must not invalidate everything. If the range is too big we
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* must use wb-inv of the entire cache.
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*/
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ENTRY(armv5_dcache_inv_range)
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ldr ip, .Larmv5_line_size
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cmp r1, #0x4000
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bcs .Larmv5_dcache_wbinv_all
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ldr ip, [ip]
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sub r1, r1, #1 /* Don't overrun */
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sub r3, ip, #1
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and r2, r0, r3
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add r1, r1, r2
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bic r0, r0, r3
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1:
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mcr p15, 0, r0, c7, c6, 1 /* Invalidate D cache SE with VA */
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add r0, r0, ip
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subs r1, r1, ip
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bpl 1b
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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RET
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ENTRY(armv5_idcache_wbinv_range)
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ldr ip, .Larmv5_line_size
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cmp r1, #0x4000
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bcs .Larmv5_idcache_wbinv_all
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ldr ip, [ip]
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sub r1, r1, #1 /* Don't overrun */
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sub r3, ip, #1
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and r2, r0, r3
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add r1, r1, r2
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bic r0, r0, r3
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1:
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mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
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mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
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add r0, r0, ip
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subs r1, r1, ip
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bpl 1b
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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RET
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ENTRY_NP(armv5_idcache_wbinv_all)
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.Larmv5_idcache_wbinv_all:
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/*
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* We assume that the code here can never be out of sync with the
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* dcache, so that we can safely flush the Icache and fall through
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* into the Dcache purging code.
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*/
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mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
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/* Fall through to purge Dcache. */
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ENTRY(armv5_dcache_wbinv_all)
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.Larmv5_dcache_wbinv_all:
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ldr ip, .Larmv5_cache_data
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ldmia ip, {s_max, i_max, s_inc, i_inc}
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1:
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orr ip, s_max, i_max
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2:
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mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */
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sub ip, ip, i_inc
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tst ip, i_max /* Index 0 is last one */
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bne 2b /* Next index */
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mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */
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subs s_max, s_max, s_inc
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bpl 1b /* Next set */
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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RET
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.Larmv5_cache_data:
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.word _C_LABEL(armv5_dcache_sets_max)
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.bss
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/* XXX The following macros should probably be moved to asm.h */
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#define _DATA_OBJECT(x) .globl x; .type x,_ASM_TYPE_OBJECT; x:
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#define C_OBJECT(x) _DATA_OBJECT(_C_LABEL(x))
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/*
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* Parameters for the cache cleaning code. Note that the order of these
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* four variables is assumed in the code above. Hence the reason for
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* declaring them in the assembler file.
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*/
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.align 0
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C_OBJECT(armv5_dcache_sets_max)
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.space 4
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C_OBJECT(armv5_dcache_index_max)
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.space 4
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C_OBJECT(armv5_dcache_sets_inc)
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.space 4
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C_OBJECT(armv5_dcache_index_inc)
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.space 4
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