255 lines
8.7 KiB
C
255 lines
8.7 KiB
C
/*
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* Copyright (c) 1988 University of Utah.
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* Copyright (c) 1982, 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: Utah Hdr: cpu.h 1.16 91/03/25
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* from: @(#)cpu.h 7.7 (Berkeley) 6/27/91
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* $Id: cpu.h,v 1.2 1993/08/01 19:23:31 mycroft Exp $
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*/
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/*
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* Exported definitions unique to amiga/68k cpu support.
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*/
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/*
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* definitions of cpu-dependent requirements
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* referenced in generic code
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*/
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#define COPY_SIGCODE /* copy sigcode above user stack in exec */
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/*
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* function vs. inline configuration;
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* these are defined to get generic functions
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* rather than inline or machine-dependent implementations
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*/
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#define NEED_MINMAX /* need {,i,l,ul}{min,max} functions */
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#undef NEED_FFS /* don't need ffs function */
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#undef NEED_BCMP /* don't need bcmp function */
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#undef NEED_STRLEN /* don't need strlen function */
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#define cpu_exec(p) /* nothing */
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#define cpu_wait(p) /* nothing */
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/*
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* Arguments to hardclock, softclock and gatherstats
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* encapsulate the previous machine state in an opaque
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* clockframe; for hp300, use just what the hardware
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* leaves on the stack.
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*/
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typedef struct intrframe {
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int pc;
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int ps;
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} clockframe;
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#define CLKF_USERMODE(framep) (((framep)->ps & PSL_S) == 0)
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#define CLKF_BASEPRI(framep) (((framep)->ps & PSL_IPL7) == 0)
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#define CLKF_PC(framep) ((framep)->pc)
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/*
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* Preempt the current process if in interrupt from user mode,
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* or after the current trap/syscall if in system mode.
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*/
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#define need_resched() { want_resched++; aston(); }
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/*
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* Give a profiling tick to the current process from the softclock
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* interrupt. On hp300, request an ast to send us through trap(),
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* marking the proc as needing a profiling tick.
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*/
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#define profile_tick(p, framep) { (p)->p_flag |= SOWEUPC; aston(); }
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/*
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* Notify the current process (p) that it has a signal pending,
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* process as soon as possible.
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*/
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#define signotify(p) aston()
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#define aston() (astpending++)
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int astpending; /* need to trap before returning to user mode */
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int want_resched; /* resched() was called */
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/*
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* simulated software interrupt register
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*/
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extern unsigned char ssir;
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#define SIR_NET 0x1
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#define SIR_CLOCK 0x2
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#define siroff(x) ssir &= ~(x)
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#define setsoftnet() ssir |= SIR_NET
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#define setsoftclock() ssir |= SIR_CLOCK
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/*
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* The rest of this should probably be moved to ../amiga/amigacpu.h,
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* although some of it could probably be put into generic 68k headers.
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*/
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/* values for machineid (happen to be AFF_* settings of AttnFlags)
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* NOTE: '40 support does NOT YET exist! */
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#define AMIGA_68020 (1L<<1)
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#define AMIGA_68030 (1L<<2)
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#define AMIGA_68040 (1L<<3)
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#define AMIGA_68881 (1L<<4)
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#define AMIGA_68882 (1L<<5)
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#define AMIGA_FPU40 (1L<<6)
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/* values for mmutype (assigned for quick testing) */
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#define MMU_68030 -1 /* 68030 on-chip subset of 68851 */
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#define MMU_68851 1 /* Motorola 68851 */
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/* values for cpuspeed (not really related to clock speed due to caches) */
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#define MHZ_8 1
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#define MHZ_16 2
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#define MHZ_25 3
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#define MHZ_33 4
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#define MHZ_50 6
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#ifdef KERNEL
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extern int machineid, mmutype;
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extern char *chipmembase, *chipmemlimit;
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extern char *customchipbase, *customchiplimit;
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/* what is this supposed to do? i.e. how is it different than startrtclock?
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#define enablertclock()
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Answer (MW): startrtclock is supposed to start the clock chip (to get an
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accurate uptime, enablertclock is called later (after *vital* stuff
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has been setup) to enable clock interrupts. Enabling clock interrupts
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at startrtclock-time can get you into big troubles... */
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#endif
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/* physical memory sections */
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#define CHIPMEMBASE (0x00000000)
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/* maximum for mapping, not the whole range is needed in physical equivalence */
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#define CHIPMEMTOP (0x00200000)
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#define CHIPMEMSIZE btoc(CHIPMEMTOP-CHIPMEMBASE)
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/* CIA-A and CIA-B */
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#define CIABASE (0x00BFC000)
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#define CIATOP (0x00C00000)
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#define CIASIZE btoc(CIATOP-CIABASE)
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#define CUSTOMBASE (0x00DFE000)
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#define CUSTOMTOP (0x00E00000)
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#define CUSTOMSIZE btoc(CUSTOMTOP-CUSTOMBASE)
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#ifdef A3000
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#define SCSIBASE (0x00DD0000)
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#define SCSITOP (0x00DD0000+AMIGA_PAGE_SIZE)
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#define SCSISIZE btoc(SCSITOP-SCSIBASE)
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#endif
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/* XXX only correct for A3000 memory map!
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* corresponds to address of last physical memory page, for A3000
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* this is always 0x08000000 - pagesize (== NBPS)
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*/
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#define MAXADDR (0x08000000 - UPAGES)
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/* Amiga specific mappings:
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*
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* phys-start map-start phys-end map-end name
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*
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* 0x00000000 chipmembase - 0x00200000 chipmemlimit CHIP MEM
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* 0x00be0000 ciabase - 0x00c00000 cialimit CIA-B/CIA-A
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* 0x00d80000 customchipbase - 0x00f00000 customchiplimit CUSTOM/ZORRO2
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*/
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#define ISCHIPMEM(va) \
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((char *)(va) >= chipmembase && (char *)(va) < chipmemlimit)
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#define CHIPMEMV(pa) ((int)(pa)-CHIPMEMBASE+(int)chipmembase)
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#define CHIPMEMP(va) ((int)(va)-(int)chipmembase+CHIPMEMBASE)
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#define CHIPMEMPOFF(pa) ((int)(pa)-CHIPMEMBASE)
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#define CHIPMEMMAPSIZE btoc(CHIPMEMTOP-CHIPMEMBASE) /* 2mb */
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#define ISCIA(va) \
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((char *)(va) >= ciabase && (char *)(va) < cialimit)
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#define CIAV(pa) ((int)(pa)-CIABASE+(int)ciabase)
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#define CIAP(va) ((int)(va)-(int)ciabase+CIABASE)
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#define CIAPOFF(pa) ((int)(pa)-CIABASE)
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#define CIAMAPSIZE btoc(CIATOP-CIABASE) /* 8k */
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#define ISCUSTOMCHIP(va) \
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((char *)(va) >= customchipbase && (char *)(va) < customchiplimit)
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#define CUSTOMCHIPV(pa) ((int)(pa)-CUSTOMCHIPBASE+(int)customchipbase)
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#define CUSTOMCHIPP(va) ((int)(va)-(int)customchipbase+CUSTOMCHIPBASE)
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#define CUSTOMCHIPPOFF(pa) ((int)(pa)-CUSTOMCHIPBASE)
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#define CUSTOMCHIPMAPSIZE btoc(CUSTOMCHIPTOP-CUSTOMCHIPBASE) /* 1.5mb */
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/*
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* 68851 and 68030 MMU
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*/
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#define PMMU_LVLMASK 0x0007
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#define PMMU_INV 0x0400
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#define PMMU_WP 0x0800
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#define PMMU_ALV 0x1000
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#define PMMU_SO 0x2000
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#define PMMU_LV 0x4000
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#define PMMU_BE 0x8000
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#define PMMU_FAULT (PMMU_WP|PMMU_INV)
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/* 680X0 function codes */
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#define FC_USERD 1 /* user data space */
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#define FC_USERP 2 /* user program space */
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#define FC_SUPERD 5 /* supervisor data space */
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#define FC_SUPERP 6 /* supervisor program space */
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#define FC_CPU 7 /* CPU space */
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/* fields in the 68020 cache control register */
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#define IC_ENABLE 0x0001 /* enable instruction cache */
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#define IC_FREEZE 0x0002 /* freeze instruction cache */
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#define IC_CE 0x0004 /* clear instruction cache entry */
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#define IC_CLR 0x0008 /* clear entire instruction cache */
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/* additional fields in the 68030 cache control register */
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#define IC_BE 0x0010 /* instruction burst enable */
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#define DC_ENABLE 0x0100 /* data cache enable */
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#define DC_FREEZE 0x0200 /* data cache freeze */
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#define DC_CE 0x0400 /* clear data cache entry */
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#define DC_CLR 0x0800 /* clear entire data cache */
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#define DC_BE 0x1000 /* data burst enable */
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#define DC_WA 0x2000 /* write allocate */
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#define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
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#define CACHE_OFF (DC_CLR|IC_CLR)
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#define CACHE_CLR (CACHE_ON)
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#define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
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#define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE)
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