267 lines
8.2 KiB
C
267 lines
8.2 KiB
C
/* $NetBSD: ichlpcib.c,v 1.3 2004/03/15 05:31:46 minoura Exp $ */
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/*-
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* Copyright (c) 2004 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Minoura Makoto.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Intel I/O Controller Hub (ICHn) LPC Interface Bridge driver
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*
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* LPC Interface Bridge is basically a pcib (PCI-ISA Bridge), but has
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* some power management and monitoring functions.
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* Currently we support the watchdog timer.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.3 2004/03/15 05:31:46 minoura Exp $");
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <machine/bus.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/sysmon/sysmonvar.h>
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#include <dev/ic/i82801lpcreg.h>
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struct lpcib_softc {
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/* Device object. */
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struct device sc_dev;
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/* Watchdog variables. */
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struct sysmon_wdog sc_smw;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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};
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static int lpcibmatch(struct device *, struct cfdata *, void *);
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static void lpcibattach(struct device *, struct device *, void *);
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static void tcotimer_configure(struct lpcib_softc *,
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struct pci_attach_args *);
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static int tcotimer_setmode(struct sysmon_wdog *);
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static int tcotimer_tickle(struct sysmon_wdog *);
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/* Defined in arch/i386/pci/pcib.c. */
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extern void pcibattach(struct device *, struct device *, void *);
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CFATTACH_DECL(ichlpcib, sizeof(struct lpcib_softc),
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lpcibmatch, lpcibattach, NULL, NULL);
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/*
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* Autoconf callbacks.
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*/
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static int
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lpcibmatch(struct device *parent, struct cfdata *match, void *aux)
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{
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struct pci_attach_args *pa = aux;
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/* We are ISA bridge, of course */
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if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE ||
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PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) {
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return 0;
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}
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/* Matches only Intel ICH */
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) {
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switch (PCI_PRODUCT(pa->pa_id)) {
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case PCI_PRODUCT_INTEL_82801AA_LPC: /* ICH */
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case PCI_PRODUCT_INTEL_82801AB_LPC: /* ICH0 */
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case PCI_PRODUCT_INTEL_82801BA_LPC: /* ICH2 */
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case PCI_PRODUCT_INTEL_82801BAM_LPC: /* ICH2-M */
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case PCI_PRODUCT_INTEL_82801CA_LPC: /* ICH3-S */
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case PCI_PRODUCT_INTEL_82801CAM_LPC: /* ICH3-M */
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case PCI_PRODUCT_INTEL_82801DB_LPC: /* ICH4 */
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case PCI_PRODUCT_INTEL_82801EB_LPC: /* ICH5 */
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return 10; /* prior to pcib */
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}
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}
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return 0;
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}
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static void
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lpcibattach(struct device *parent, struct device *self, void *aux)
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{
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struct pci_attach_args *pa = aux;
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struct lpcib_softc *sc = (void*) self;
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pcibattach(parent, self, aux);
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/* Currently we use TCO timer feature only... */
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tcotimer_configure(sc, pa);
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}
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/*
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* Initialize the watchdog timer.
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*/
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static void
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tcotimer_configure(struct lpcib_softc *sc, struct pci_attach_args *pa)
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{
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pcireg_t pcireg;
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unsigned int ioreg;
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sc->sc_smw.smw_name = sc->sc_dev.dv_xname;
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sc->sc_smw.smw_cookie = sc;
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sc->sc_smw.smw_setmode = tcotimer_setmode;
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sc->sc_smw.smw_tickle = tcotimer_tickle;
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sc->sc_smw.smw_period =
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lpcib_tcotimer_tick_to_second(LPCIB_TCOTIMER_MAX_TICK);
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if (sysmon_wdog_register(&sc->sc_smw)) {
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printf("%s: unable to register TCO timer"
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"as a sysmon watchdog device.\n",
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sc->sc_dev.dv_xname);
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return;
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}
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/*
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* Part of our I/O registers are used as ACPI PM regs.
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* Since our ACPI subsystem accesses the I/O space directly so far,
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* we do not have to bother bus_space I/O map confliction.
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*/
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if (pci_mapreg_map(pa, LPCIB_PCI_PMBASE, PCI_MAPREG_TYPE_IO, 0,
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&sc->sc_iot, &sc->sc_ioh, NULL, NULL)) {
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sysmon_wdog_unregister(&sc->sc_smw);
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printf("%s: can't map i/o space; "
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"TCO timer disabled\n", sc->sc_dev.dv_xname);
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return;
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}
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/* Explicitly stop the TCO timer. */
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ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT);
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if ((ioreg & LPCIB_TCO1_CNT_TCO_TMR_HLT) == 0)
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bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT,
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ioreg | LPCIB_TCO1_CNT_TCO_TMR_HLT);
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/*
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* Enable TCO timeout SMI. SMBIOS might ignore it, but...
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*/
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ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN);
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if (ioreg & LPCIB_SMI_EN_GBL_SMI_EN)
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN,
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ioreg | LPCIB_SMI_EN_TCO_EN);
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/*
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* And enable TCO timeout reset.
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* This logic works when the TCO timer expires twice.
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*/
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pcireg = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_PCI_GEN_STA);
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if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT) {
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/* TCO timeout reset is disabled; try to enable it */
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pci_conf_write(pa->pa_pc, pa->pa_tag, LPCIB_PCI_GEN_STA,
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pcireg & (~LPCIB_PCI_GEN_STA_NO_REBOOT));
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pcireg = pci_conf_read(pa->pa_pc, pa->pa_tag,
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LPCIB_PCI_GEN_STA);
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if (pcireg & LPCIB_PCI_GEN_STA_NO_REBOOT)
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printf("%s: TCO timer reboot disabled by hardware; "
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"hope SMBIOS properly handle it.\n",
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sc->sc_dev.dv_xname);
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}
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printf("%s: TCO (watchdog) timer configured.\n", sc->sc_dev.dv_xname);
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return;
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}
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/*
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* Sysmon watchdog callbacks.
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*/
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static int
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tcotimer_setmode(struct sysmon_wdog *smw)
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{
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struct lpcib_softc *sc = smw->smw_cookie;
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unsigned int ioreg, period;
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if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) {
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/* Stop the TCO timer. */
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ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh,
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LPCIB_TCO1_CNT);
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if ((ioreg & LPCIB_TCO1_CNT_TCO_TMR_HLT) == 0)
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bus_space_write_2(sc->sc_iot, sc->sc_ioh,
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LPCIB_TCO1_CNT,
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ioreg | LPCIB_TCO1_CNT_TCO_TMR_HLT);
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} else {
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if (smw->smw_period == WDOG_PERIOD_DEFAULT) {
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period = LPCIB_TCOTIMER_MAX_TICK;
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smw->smw_period =
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lpcib_tcotimer_tick_to_second(period);
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} else
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period = lpcib_tcotimer_second_to_tick(smw->smw_period);
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if (period < LPCIB_TCOTIMER_MIN_TICK ||
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period > LPCIB_TCOTIMER_MAX_TICK)
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return EINVAL;
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/* Stop the TCO timer, */
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ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh,
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LPCIB_TCO1_CNT);
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if ((ioreg & LPCIB_TCO1_CNT_TCO_TMR_HLT) == 0)
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bus_space_write_2(sc->sc_iot, sc->sc_ioh,
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LPCIB_TCO1_CNT,
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ioreg | LPCIB_TCO1_CNT_TCO_TMR_HLT);
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/* set the timeout, */
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period |= (bus_space_read_1(sc->sc_iot, sc->sc_ioh,
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LPCIB_TCO_TMR) & ~LPCIB_TCO_TMR_MASK);
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bus_space_write_1(sc->sc_iot, sc->sc_ioh,
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LPCIB_TCO_TMR, period);
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/* and restart the timer. */
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bus_space_write_2(sc->sc_iot, sc->sc_ioh,
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LPCIB_TCO1_CNT,
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ioreg & ~LPCIB_TCO1_CNT_TCO_TMR_HLT);
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tcotimer_tickle(smw);
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}
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return 0;
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}
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static int
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tcotimer_tickle(struct sysmon_wdog *smw)
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{
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struct lpcib_softc *sc = smw->smw_cookie;
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/* any value is allowed */
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bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 0);
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return 0;
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}
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