275 lines
7.5 KiB
C
275 lines
7.5 KiB
C
/* $NetBSD: ixp425_pci.c,v 1.3 2003/12/08 13:40:33 scw Exp $ */
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/*
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* Copyright (c) 2003
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* Ichiro FUKUHARA <ichiro@ichiro.org>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Ichiro FUKUHARA.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ixp425_pci.c,v 1.3 2003/12/08 13:40:33 scw Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/extent.h>
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#include <sys/malloc.h>
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#include <uvm/uvm_extern.h>
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#include <machine/bus.h>
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#include <arm/xscale/ixp425reg.h>
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#include <arm/xscale/ixp425var.h>
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#include <evbarm/ixdp425/ixdp425reg.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pciconf.h>
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#include "opt_pci.h"
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#include "pci.h"
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void ixp425_pci_attach_hook(struct device *, struct device *,
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struct pcibus_attach_args *);
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int ixp425_pci_bus_maxdevs(void *, int);
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void ixp425_pci_decompose_tag(void *, pcitag_t, int *, int *, int *);
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void ixp425_pci_conf_setup(void *, struct ixp425_softc *, pcitag_t, int);
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void ixp425_pci_conf_write(void *, pcitag_t, int, pcireg_t);
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pcitag_t ixp425_pci_make_tag(void *, int, int, int);
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pcireg_t ixp425_pci_conf_read(void *, pcitag_t, int);
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#define MAX_PCI_DEVICES 32
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void
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ixp425_pci_init(struct ixp425_softc *sc)
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{
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pci_chipset_tag_t pc = &sc->ia_pci_chipset;
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#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
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struct extent *ioext, *memext;
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#endif
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/*
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* Initialise the PCI chipset tag
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*/
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pc->pc_conf_v = sc;
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pc->pc_attach_hook = ixp425_pci_attach_hook;
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pc->pc_bus_maxdevs = ixp425_pci_bus_maxdevs;
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pc->pc_make_tag = ixp425_pci_make_tag;
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pc->pc_decompose_tag = ixp425_pci_decompose_tag;
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pc->pc_conf_read = ixp425_pci_conf_read;
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pc->pc_conf_write = ixp425_pci_conf_write;
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/*
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* Initialize the bus space tags.
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*/
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ixp425_io_bs_init(&sc->sc_pci_iot, sc);
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ixp425_mem_bs_init(&sc->sc_pci_memt, sc);
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#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
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ioext = extent_create("pciio", 0, IXP425_PCI_IO_SIZE - 1,
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M_DEVBUF, NULL, 0, EX_NOWAIT);
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/* PCI MEM space is mapped same address as real memory */
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memext = extent_create("pcimem", IXP425_PCI_MEM_HWBASE,
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IXP425_PCI_MEM_HWBASE +
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IXP425_PCI_MEM_SIZE - 1,
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M_DEVBUF, NULL, 0, EX_NOWAIT);
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printf("%s: configuring PCI bus\n", sc->sc_dev.dv_xname);
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pci_configure_bus(pc, ioext, memext, NULL, 0 /* XXX bus = 0 */,
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arm_dcache_align);
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extent_destroy(ioext);
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extent_destroy(memext);
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#endif
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}
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void
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pci_conf_interrupt(pci_chipset_tag_t pc, int a, int b, int c, int d, int *p)
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{
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}
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void
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ixp425_pci_attach_hook(struct device *parent, struct device *self,
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struct pcibus_attach_args *pba)
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{
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/* Nothing to do. */
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}
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int
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ixp425_pci_bus_maxdevs(void *v, int busno)
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{
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return(MAX_PCI_DEVICES);
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}
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pcitag_t
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ixp425_pci_make_tag(void *v, int bus, int device, int function)
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{
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#ifdef PCI_DEBUG
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printf("ixp425_pci_make_tag(v=%p, bus=%d, device=%d, function=%d)\n",
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v, bus, device, function);
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#endif
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return ((bus << 16) | (device << 11) | (function << 8));
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}
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void
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ixp425_pci_decompose_tag(void *v, pcitag_t tag, int *busp, int *devicep,
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int *functionp)
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{
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#ifdef PCI_DEBUG
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printf("ixp425_pci_decompose_tag(v=%p, tag=0x%08lx, bp=%x, dp=%x, fp=%x)\n",
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v, tag, (int)busp, (int)devicep, (int)functionp);
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#endif
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if (busp != NULL)
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*busp = (tag >> 16) & 0xff;
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if (devicep != NULL)
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*devicep = (tag >> 11) & 0x1f;
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if (functionp != NULL)
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*functionp = (tag >> 8) & 0x7;
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}
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void
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ixp425_pci_conf_setup(void *v, struct ixp425_softc *sc, pcitag_t tag, int offset)
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{
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int bus, device, function;
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ixp425_pci_decompose_tag(v, tag, &bus, &device, &function);
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if (bus == 0) {
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if (device == 0 && function == 0) {
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PCI_CSR_WRITE_4(sc, PCI_NP_AD, (offset & ~3));
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} else {
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/* configuration type 0 */
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PCI_CSR_WRITE_4(sc, PCI_NP_AD, (1U << (32 - device)) |
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(function << 8) | (offset & ~3));
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}
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} else {
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/* configuration type 1 */
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PCI_CSR_WRITE_4(sc, PCI_NP_AD,
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(bus << 16) | (device << 11) |
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(function << 8) | (offset & ~3) | 1);
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}
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}
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/* read/write PCI Non-Pre-fetch Data */
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pcireg_t
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ixp425_pci_conf_read(void *v, pcitag_t tag, int offset)
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{
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struct ixp425_softc *sc = v;
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u_int32_t data;
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pcireg_t rv;
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int s;
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#define PCI_NP_HAVE_BUG
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#ifdef PCI_NP_HAVE_BUG
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int i;
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#endif
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PCI_CONF_LOCK(s);
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ixp425_pci_conf_setup(v, sc, tag, offset);
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#ifdef PCI_DEBUG
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printf("ixp425_pci_conf_read: tag=%lx,offset=%x\n",
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tag, offset);
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#endif
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#ifdef PCI_NP_HAVE_BUG
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/* PCI NP Bug workaround */
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for (i = 0; i < 8; i++) {
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PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_READ);
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rv = PCI_CSR_READ_4(sc, PCI_NP_RDATA);
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rv = PCI_CSR_READ_4(sc, PCI_NP_RDATA);
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}
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#else
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PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_READ);
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rv = PCI_CSR_READ_4(sc, PCI_NP_RDATA);
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#endif
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/* check&clear PCI abort */
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data = PCI_CSR_READ_4(sc, PCI_ISR);
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if (data & ISR_PFE) {
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PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE);
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PCI_CONF_UNLOCK(s);
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return -1;
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} else {
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PCI_CONF_UNLOCK(s);
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return rv;
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}
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}
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void
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ixp425_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val)
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{
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struct ixp425_softc *sc = v;
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u_int32_t data;
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int s;
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PCI_CONF_LOCK(s);
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ixp425_pci_conf_setup(v, sc, tag, offset);
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#ifdef PCI_DEBUG
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printf("ixp425_pci_conf_write: tag=%lx offset=%x <- val=%x\n",
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tag, offset, val);
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#endif
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PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_WRITE);
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PCI_CSR_WRITE_4(sc, PCI_NP_WDATA, val);
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/* check&clear PCI abort */
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data = PCI_CSR_READ_4(sc, PCI_ISR);
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if (data & ISR_PFE)
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PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE);
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PCI_CONF_UNLOCK(s);
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}
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/* read/write pci configuration data */
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uint32_t
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ixp425_pci_conf_reg_read(struct ixp425_softc *sc, uint32_t reg)
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{
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uint32_t data;
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bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
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PCI_CRP_AD_CBE, ((reg & ~3) | COMMAND_CRP_READ));
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data = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh,
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PCI_CRP_AD_RDATA);
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return data;
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}
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void
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ixp425_pci_conf_reg_write(struct ixp425_softc *sc, uint32_t reg,
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uint32_t data)
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{
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bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
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PCI_CRP_AD_CBE, ((reg & ~3) | COMMAND_CRP_WRITE));
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bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
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PCI_CRP_AD_WDATA, data);
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}
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