270 lines
7.7 KiB
C
270 lines
7.7 KiB
C
/* $NetBSD: s3c2xx0_intr.c,v 1.8 2003/12/17 13:20:04 bsh Exp $ */
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/*
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* Copyright (c) 2002, 2003 Fujitsu Component Limited
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* Copyright (c) 2002, 2003 Genetec Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of The Fujitsu Component Limited nor the name of
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* Genetec corporation may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
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* CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
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* CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Common part of IRQ handlers for Samsung S3C2800/2400/2410 processors.
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* derived from i80321_icu.c
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*/
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/*
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* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: s3c2xx0_intr.c,v 1.8 2003/12/17 13:20:04 bsh Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <uvm/uvm_extern.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <arm/cpufunc.h>
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#include <arm/s3c2xx0/s3c2xx0reg.h>
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#include <arm/s3c2xx0/s3c2xx0var.h>
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volatile uint32_t *s3c2xx0_intr_mask_reg;
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static __inline void
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__raise(int ipl)
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{
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if (current_spl_level < ipl) {
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s3c2xx0_setipl(ipl);
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}
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}
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/*
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* modify interrupt mask table for SPL levels
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*/
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void
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s3c2xx0_update_intr_masks(int irqno, int level)
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{
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int mask = 1 << irqno;
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int i;
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s3c2xx0_ilevel[irqno] = level;
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for (i = 0; i < level; ++i)
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s3c2xx0_imask[i] |= mask; /* Enable interrupt at lower
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* level */
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for (; i < NIPL - 1; ++i)
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s3c2xx0_imask[i] &= ~mask; /* Disable itnerrupt at upper
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* level */
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/*
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* Enforce a heirarchy that gives "slow" device (or devices with
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* limited input buffer space/"real-time" requirements) a better
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* chance at not dropping data.
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*/
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s3c2xx0_imask[IPL_BIO] &= s3c2xx0_imask[IPL_SOFTNET];
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s3c2xx0_imask[IPL_NET] &= s3c2xx0_imask[IPL_BIO];
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s3c2xx0_imask[IPL_SOFTSERIAL] &= s3c2xx0_imask[IPL_NET];
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s3c2xx0_imask[IPL_TTY] &= s3c2xx0_imask[IPL_SOFTSERIAL];
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/*
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* splvm() blocks all interrupts that use the kernel memory
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* allocation facilities.
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*/
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s3c2xx0_imask[IPL_VM] &= s3c2xx0_imask[IPL_TTY];
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/*
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* Audio devices are not allowed to perform memory allocation
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* in their interrupt routines, and they have fairly "real-time"
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* requirements, so give them a high interrupt priority.
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*/
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s3c2xx0_imask[IPL_AUDIO] &= s3c2xx0_imask[IPL_VM];
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/*
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* splclock() must block anything that uses the scheduler.
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*/
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s3c2xx0_imask[IPL_CLOCK] &= s3c2xx0_imask[IPL_AUDIO];
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/*
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* splhigh() must block "everything".
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*/
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s3c2xx0_imask[IPL_HIGH] &= s3c2xx0_imask[IPL_STATCLOCK];
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/*
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* XXX We need serial drivers to run at the absolute highest priority
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* in order to avoid overruns, so serial > high.
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*/
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s3c2xx0_imask[IPL_SERIAL] &= s3c2xx0_imask[IPL_HIGH];
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}
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void
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s3c2xx0_do_pending(int enable_int)
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{
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static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED;
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int oldirqstate, irqstate, spl_save;
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if (__cpu_simple_lock_try(&processing) == 0)
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return;
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spl_save = current_spl_level;
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oldirqstate = irqstate = disable_interrupts(I32_bit);
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if (enable_int)
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irqstate &= ~I32_bit;
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#define DO_SOFTINT(si,ipl) \
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if (get_pending_softint() & SI_TO_IRQBIT(si)) { \
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softint_pending &= ~SI_TO_IRQBIT(si); \
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__raise(ipl); \
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restore_interrupts(irqstate); \
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softintr_dispatch(si); \
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disable_interrupts(I32_bit); \
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s3c2xx0_setipl(spl_save); \
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}
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do {
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DO_SOFTINT(SI_SOFTSERIAL, IPL_SOFTSERIAL);
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DO_SOFTINT(SI_SOFTNET, IPL_SOFTNET);
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DO_SOFTINT(SI_SOFTCLOCK, IPL_SOFTCLOCK);
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DO_SOFTINT(SI_SOFT, IPL_SOFT);
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} while (get_pending_softint());
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__cpu_simple_unlock(&processing);
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restore_interrupts(oldirqstate);
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}
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static int
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stray_interrupt(void *cookie)
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{
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int save;
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int irqno = (int) cookie;
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printf("stray interrupt %d\n", irqno);
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save = disable_interrupts(I32_bit);
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*s3c2xx0_intr_mask_reg &= ~(1U << irqno);
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restore_interrupts(save);
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return 0;
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}
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/*
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* Initialize interrupt dispatcher.
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*/
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void
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s3c2xx0_intr_init(struct s3c2xx0_intr_dispatch * dispatch_table, int icu_len)
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{
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int i;
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for (i = 0; i < icu_len; ++i) {
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dispatch_table[i].func = stray_interrupt;
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dispatch_table[i].cookie = (void *) (i);
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dispatch_table[i].level = IPL_BIO;
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}
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global_intr_mask = ~0; /* no intr is globally blocked. */
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_splraise(IPL_SERIAL);
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enable_interrupts(I32_bit);
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}
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/*
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* initialize variables so that splfoo() doesn't touch illegal address.
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* called during bootstrap.
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*/
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void
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s3c2xx0_intr_bootstrap(vaddr_t icureg)
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{
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s3c2xx0_intr_mask_reg = (volatile uint32_t *)(icureg + INTCTL_INTMSK);
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}
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#undef splx
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void
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splx(int ipl)
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{
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s3c2xx0_splx(ipl);
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}
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#undef _splraise
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int
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_splraise(int ipl)
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{
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return s3c2xx0_splraise(ipl);
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}
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#undef _spllower
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int
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_spllower(int ipl)
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{
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return s3c2xx0_spllower(ipl);
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}
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#undef _setsoftintr
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void
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_setsoftintr(int si)
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{
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return s3c2xx0_setsoftintr(si);
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}
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