326 lines
13 KiB
C
326 lines
13 KiB
C
/* $NetBSD: stp4020reg.h,v 1.4 2008/04/28 20:23:57 martin Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Paul Kranenburg.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _STP4020_REG_H
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#define _STP4020_REG_H
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/*
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* STP4020: SBus/PCMCIA bridge supporting two Type-3 PCMCIA cards.
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* Programming information source:
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* - http://www.sun.com/microelectronics/datasheets/stp4020/
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* - SunOS 5.5 header file
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*/
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/*
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* General chip attibutes.
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*/
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#define STP4020_NSOCK 2 /* number of PCCARD sockets per STP4020 */
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#define STP4020_NWIN 3 /* number of windows per socket */
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/*
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* Socket control registers.
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*
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* Each PCMCIA socket has two interface control registers and two interface
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* status registers associated with it.
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*/
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/*
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* Socket Interface Control register 0
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*/
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#define STP4020_ICR0_rsvd1 0xc000 /* reserved bits */
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#define STP4020_ICR0_PROMEN 0x2000 /* FCode PROM enable */
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/* Status change interrupts can be routed to one of two SBus interrupt levels:*/
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#define STP4020_ICR0_SCILVL 0x1000 /* card status change interrupt level */
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#define STP4020_ICR0_SCILVL_SB0 0x0000 /* interrupt on *SB_INT[0] */
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#define STP4020_ICR0_SCILVL_SB1 0x1000 /* interrupt on *SB_INT[1] */
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/* Interrupt enable bits: */
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#define STP4020_ICR0_CDIE 0x0800 /* card detect interrupt enable */
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#define STP4020_ICR0_BVD2IE 0x0400 /* battery voltage detect 2 int en. */
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#define STP4020_ICR0_BVD1IE 0x0200 /* battery voltage detect 1 int en. */
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#define STP4020_ICR0_RDYIE 0x0100 /* ready/busy interrupt enable */
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#define STP4020_ICR0_WPIE 0x0080 /* write protect interrupt enable */
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#define STP4020_ICR0_CTOIE 0x0040 /* PC card timeout interrupt enable */
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#define STP4020_ICR0_rsvd2 0x0020 /* */
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#define STP4020_ICR0_IOIE 0x0010 /* I/O (*IRQ) interrupt enable */
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/* PC card I/O interrupts can also be routed to one of two SBus intr levels: */
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#define STP4020_ICR0_IOILVL 0x0008 /* I/O (*IRQ) interrupt level (SBus) */
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#define STP4020_ICR0_IOILVL_SB0 0x0000 /* interrupt on *SB_INT[0] */
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#define STP4020_ICR0_IOILVL_SB1 0x0008 /* interrupt on *SB_INT[1] */
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#define STP4020_ICR0_SPKREN 0x0004 /* *SPKR_OUT enable */
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#define STP4020_ICR0_RESET 0x0002 /* PC card reset */
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#define STP4020_ICR0_IFTYPE 0x0001 /* PC card interface type */
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#define STP4020_ICR0_IFTYPE_MEM 0x0000 /* MEMORY only */
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#define STP4020_ICR0_IFTYPE_IO 0x0001 /* MEMORY and I/O */
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#define STP4020_ICR0_BITS "\177\010" \
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"b\0IFTYPE\0b\1RESET\0b\2SPKREN\0" \
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"b\3IOILVL\0b\4IOIE\0b\6CTOIE\0" \
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"b\7WPIE\0b\10RDYIE\0b\11BVD1IE\0b\12BVD2IE\0"\
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"b\13CDIE\0b\14SCILV\0b\15PROMEN\0\0"
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/* Shorthand for all status change interrupts enables */
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#define STP4020_ICR0_ALL_STATUS_IE ( \
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STP4020_ICR0_CDIE | \
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STP4020_ICR0_BVD2IE | \
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STP4020_ICR0_BVD1IE | \
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STP4020_ICR0_RDYIE | \
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STP4020_ICR0_WPIE | \
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STP4020_ICR0_CTOIE \
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)
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/*
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* Socket Interface Control register 1
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*/
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#define STP4020_ICR1_LPBKEN 0x8000 /* PC card data loopback enable */
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#define STP4020_ICR1_CD1DB 0x4000 /* card detect 1 diagnostic bit */
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#define STP4020_ICR1_BVD2DB 0x2000 /* battery voltage detect 2 diag bit */
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#define STP4020_ICR1_BVD1DB 0x1000 /* battery voltage detect 1 diag bit */
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#define STP4020_ICR1_RDYDB 0x0800 /* ready/busy diagnostic bit */
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#define STP4020_ICR1_WPDB 0x0400 /* write protect diagnostic bit */
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#define STP4020_ICR1_WAITDB 0x0200 /* *WAIT diagnostic bit */
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#define STP4020_ICR1_DIAGEN 0x0100 /* diagnostic enable bit */
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#define STP4020_ICR1_rsvd1 0x0080 /* reserved */
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#define STP4020_ICR1_APWREN 0x0040 /* PC card auto power switch enable */
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/*
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* The Vpp controls are two-bit fields which specify which voltage
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* should be switched onto Vpp for this socket.
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*
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* Both of the "no connect" states are equal.
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*/
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#define STP4020_ICR1_VPP2EN 0x0030 /* Vpp2 power enable */
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#define STP4020_ICR1_VPP2_OFF 0x0000 /* no connect */
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#define STP4020_ICR1_VPP2_VCC 0x0010 /* Vcc switched onto Vpp2 */
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#define STP4020_ICR1_VPP2_VPP 0x0020 /* Vpp switched onto Vpp2 */
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#define STP4020_ICR1_VPP2_ZIP 0x0030 /* no connect */
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#define STP4020_ICR1_VPP1EN 0x000c /* Vpp1 power enable */
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#define STP4020_ICR1_VPP1_OFF 0x0000 /* no connect */
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#define STP4020_ICR1_VPP1_VCC 0x0004 /* Vcc switched onto Vpp1 */
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#define STP4020_ICR1_VPP1_VPP 0x0008 /* Vpp switched onto Vpp1 */
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#define STP4020_ICR1_VPP1_ZIP 0x000c /* no connect */
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#define STP4020_ICR1_MSTPWR 0x0002 /* PC card master power enable */
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#define STP4020_ICR1_PCIFOE 0x0001 /* PC card interface output enable */
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#define STP4020_ICR1_BITS "\177\010" \
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"b\0PCIFOE\0b\1MSTPWR\0f\2\2VPP1EN\0" \
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"f\4\2VPP2EN\0b\6APWREN\0b\10DIAGEN\0" \
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"b\11WAITDB\0b\12WPDB\0b\13RDYDB\0" \
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"b\14BVD1D\0b\15BVD2D\0\16CD1DB\0b\17LPBKEN\0"
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/*
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* Socket Interface Status register 0
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*
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* Some signals in this register change meaning depending on whether
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* the socket is configured as MEMORY-ONLY or MEMORY & I/O:
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* mo: valid only if the socket is in memory-only mode
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* io: valid only if the socket is in memory and I/O mode.
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*
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* Pending interrupts are cleared by writing the corresponding status
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* bit set in the upper half of this register.
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*/
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#define STP4020_ISR0_ZERO 0x8000 /* always reads back as zero (mo) */
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#define STP4020_ISR0_IOINT 0x8000 /* PC card I/O intr (*IRQ) posted (io)*/
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#define STP4020_ISR0_SCINT 0x4000 /* status change interrupt posted */
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#define STP4020_ISR0_CDCHG 0x2000 /* card detect status change */
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#define STP4020_ISR0_BVD2CHG 0x1000 /* battery voltage detect 2 status change */
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#define STP4020_ISR0_BVD1CHG 0x0800 /* battery voltage detect 1 status change */
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#define STP4020_ISR0_RDYCHG 0x0400 /* ready/busy status change */
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#define STP4020_ISR0_WPCHG 0x0200 /* write protect status change */
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#define STP4020_ISR0_PCTO 0x0100 /* PC card access timeout */
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#define STP4020_ISR0_LIVE 0x00ff /* live status bit mask */
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#define STP4020_ISR0_CD2ST 0x0080 /* card detect 2 live status */
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#define STP4020_ISR0_CD1ST 0x0040 /* card detect 1 live status */
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#define STP4020_ISR0_BVD2ST 0x0020 /* battery voltage detect 2 live status (mo) */
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#define STP4020_ISR0_SPKR 0x0020 /* SPKR signal live status (io)*/
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#define STP4020_ISR0_BVD1ST 0x0010 /* battery voltage detect 1 live status (mo) */
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#define STP4020_ISR0_STSCHG 0x0010 /* I/O *STSCHG signal live status (io)*/
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#define STP4020_ISR0_RDYST 0x0008 /* ready/busy live status (mo) */
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#define STP4020_ISR0_IOREQ 0x0008 /* I/O *REQ signal live status (io) */
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#define STP4020_ISR0_WPST 0x0004 /* write protect live status (mo) */
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#define STP4020_ISR0_IOIS16 0x0004 /* IOIS16 signal live status (io) */
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#define STP4020_ISR0_WAITST 0x0002 /* wait signal live status */
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#define STP4020_ISR0_PWRON 0x0001 /* PC card power status */
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#define STP4020_ISR0_IOBITS "\177\010" \
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"b\0PWRON\0b\1WAITST\0b\2IOIS16\0b\3IOREQ\0" \
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"b\4STSCHG\0b\5SPKR\0b\6CD1ST\0b\7CD2ST\0" \
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"b\10PCTO\0b\11WPCHG\0b\12RDYCHG\0" \
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"b\13BVD1CHG\0b\14BVD2CHG\0b\15CDCHG\0" \
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"b\16SCINT\0b\17IOINT\0\0"
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#define STP4020_ISR0_MOBITS "\177\010" \
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"b\0PWRON\0b\1WAITST\0b\2WPST\0b\3RDYST\0" \
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"b\4BVD1ST\0b\5BVD2ST\0b\6CD1ST\0b\7CD2ST\0" \
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"b\10PCTO\0b\11WPCHG\0b\12RDYCHG\0" \
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"b\13BVD1CHG\0b\14BVD2CHG\0b\15CDCHG\0" \
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"b\16SCINT\0\0"
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/*
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* Socket Interface Status register 1
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*/
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#define STP4020_ISR1_rsvd 0xffc0 /* reserved */
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#define STP4020_ISR1_PCTYPE_M 0x0030 /* PC card type(s) supported bit mask */
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#define STP4020_ISR1_PCTYPE_S 4 /* PC card type(s) supported bit shift */
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#define STP4020_ISR1_REV_M 0x000f /* ASIC revision level bit mask */
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#define STP4020_ISR1_REV_S 0 /* ASIC revision level bit shift */
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#define STP4020_ISR1_BITS "\177\010" \
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"f\0\4REV\0f\4\2PCTYPE\0\0" \
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/*
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* Socket window control/status register definitions.
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*
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* According to SunOS 5.5:
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* "Each PCMCIA socket has three windows associated with it; each of
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* these windows can be programmed to map in either the AM, CM or IO
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* space on the PC card. Each window can also be programmed with a
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* starting or base address relative to the PC card's address zero.
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* Each window is a fixed 1Mb in size.
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*
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* Each window has two window control registers associated with it to
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* control the window's PCMCIA bus timing parameters, PC card address
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* space that that window maps, and the base address in the
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* selected PC card's address space."
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*/
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#define STP4020_WINDOW_SIZE (1024*1024) /* 1MB */
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#define STP4020_WINDOW_SHIFT 20 /* for 1MB */
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/*
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* PC card Window Control register 0
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*/
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#define STP4020_WCR0_rsvd 0x8000 /* reserved */
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#define STP4020_WCR0_CMDLNG_M 0x7c00 /* command strobe length bit mask */
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#define STP4020_WCR0_CMDLNG_S 10 /* command strobe length bit shift */
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#define STP4020_WCR0_CMDDLY_M 0x0300 /* command strobe delay bit mask */
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#define STP4020_WCR0_CMDDLY_S 8 /* command strobe delay bit shift */
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#define STP4020_MEM_SPEED_MIN 100
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#define STP4020_MEM_SPEED_MAX 1370
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/*
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* The ASPSEL (Address Space Select) bits control which of the three PC card
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* address spaces this window maps in.
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*/
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#define STP4020_WCR0_ASPSEL_M 0x00c0 /* address space select bit mask */
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#define STP4020_WCR0_ASPSEL_AM 0x0000 /* attribute memory */
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#define STP4020_WCR0_ASPSEL_CM 0x0040 /* common memory */
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#define STP4020_WCR0_ASPSEL_IO 0x0080 /* I/O */
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/*
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* The base address controls which 1MB range in the 64MB card address space
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* this window maps to.
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*/
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#define STP4020_WCR0_BASE_M 0x0003f /* base address bit mask */
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#define STP4020_WCR0_BASE_S 0 /* base address bit shift */
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#define STP4020_ADDR2PAGE(x) ((x) >> 20)
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/*
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* PC card Window Control register 1
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*/
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#define STP4020_WCR1_rsvd 0xffe0 /* reserved */
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#define STP4020_WCR1_RECDLY_M 0x0018 /* recovery delay bit mask */
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#define STP4020_WCR1_RECDLY_S 3 /* recovery delay bit shift */
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#define STP4020_WCR1_WAITDLY_M 0x0006 /* *WAIT signal delay bit mask */
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#define STP4020_WCR1_WAITDLY_S 1 /* *WAIT signal delay bit shift */
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#define STP4020_WCR1_WAITREQ_M 0x0001 /* *WAIT signal is required bit mask */
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#define STP4020_WCR1_WAITREQ_S 0 /* *WAIT signal is required bit shift */
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#if for_reference_only
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/*
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* STP4020 CSR structures
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*
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* There is one stp4020_regs_t structure per instance, and it refers to
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* the complete Stp4020 register set.
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*
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* For each socket, there is one stp4020_socket_csr_t structure, which
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* refers to all the registers for that socket. That structure is
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* made up of the window register structures as well as the registers
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* that control overall socket operation.
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*
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* For each window, there is one stp4020_window_ctl_t structure, which
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* refers to all the registers for that window.
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*/
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/*
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* per-window CSR structure
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*/
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typedef struct stp4020_window_ctl_t {
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volatile ushort_t ctl0; /* window control register 0 */
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volatile ushort_t ctl1; /* window control register 1 */
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} stp4020_window_ctl_t;
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/*
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* per-socket CSR structure
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*/
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typedef struct stp4020_socket_csr_t {
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volatile struct stp4020_window_ctl_t window[STP4020_NWIN];
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volatile ushort_t ctl0; /* socket control register 0 */
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volatile ushort_t ctl1; /* socket control register 1 */
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volatile ushort_t stat0; /* socket status register 0 */
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volatile ushort_t stat1; /* socket status register 1 */
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volatile uchar_t filler[12]; /* filler space */
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} stp4020_socket_csr_t;
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/*
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* per-instance CSR structure
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*/
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typedef struct stp4020_regs_t {
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struct stp4020_socket_csr_t socket[STP4020_NSOCK]; /* socket CSRs */
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} stp4020_regs_t;
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#endif /* reference */
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/* Size of control and status register banks */
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#define STP4020_SOCKREGS_SIZE 32
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#define STP4020_WINREGS_SIZE 4
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/* Relative socket control & status register offsets */
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#define STP4020_ICR0_IDX 12
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#define STP4020_ICR1_IDX 14
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#define STP4020_ISR0_IDX 16
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#define STP4020_ISR1_IDX 18
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/* Relative Window control register offsets */
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#define STP4020_WCR0_IDX 0
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#define STP4020_WCR1_IDX 2
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/* Socket control and status register offsets */
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#define STP4020_ICR0_REG(s) ((32 * (s)) + STP4020_ICR0_IDX)
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#define STP4020_ICR1_REG(s) ((32 * (s)) + STP4020_ICR1_IDX)
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#define STP4020_ISR0_REG(s) ((32 * (s)) + STP4020_ISR0_IDX)
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#define STP4020_ISR1_REG(s) ((32 * (s)) + STP4020_ISR1_IDX)
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/* Window control and status registers; one set per socket */
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#define STP4020_WCR0_REG(s,w) ((32 * (s)) + (4 * (w)) + STP4020_WCR0_IDX)
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#define STP4020_WCR1_REG(s,w) ((32 * (s)) + (4 * (w)) + STP4020_WCR1_IDX)
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#endif /* _STP4020_REG_H */
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