112 lines
3.7 KiB
C
112 lines
3.7 KiB
C
/* $NetBSD: ixp12x0var.h,v 1.1 2002/07/15 16:27:17 ichiro Exp $ */
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/*
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* Copyright (c) 2002
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* Ichiro FUKUHARA <ichiro@ichiro.org>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Ichiro FUKUHARA.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _IXP12X0VAR_H_
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#define _IXP12X0VAR_H_
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#include <sys/conf.h>
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#include <sys/device.h>
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#include <sys/queue.h>
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#include <machine/bus.h>
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#include <dev/pci/pcivar.h>
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#define IXPREG(reg) *((volatile u_int32_t*) (reg))
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struct ixp12x0_softc {
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struct device sc_dev;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh; /* IRQ handle */
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u_int32_t sc_intrmask;
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/* Handles for the various subregions. */
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bus_space_handle_t sc_pci_ioh;
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/* I/O window vaddr */
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/* PCI address */
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/* Bus space, DMA, and PCI tags for the PCI bus */
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struct bus_space ia_pci_iot;
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struct bus_space ia_pci_memt;
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struct arm32_bus_dma_tag ia_pci_dmat;
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struct arm32_pci_chipset ia_pci_chipset;
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/* GPIO */
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};
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struct intrhand {
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TAILQ_ENTRY(intrhand) ih_list; /* link on intrq list */
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int (*ih_func)(void *); /* interrupt handler */
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void *ih_arg; /* arg for handler */
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int ih_ipl; /* IPL_* */
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int ih_irq; /* IRQ number */
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};
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#define IRQNAMESIZE sizeof("ixpintr ipl xxx")
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struct intrq {
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TAILQ_HEAD(, intrhand) iq_list; /* handler list */
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struct evcnt iq_ev; /* event counter */
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u_int32_t iq_mask; /* IRQs to mask while handling */
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u_int32_t iq_pci_mask; /* PCI IRQs to mask while handling */
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u_int32_t iq_levels; /* IPL_*'s this IRQ has */
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char iq_name[IRQNAMESIZE]; /* interrupt name */
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};
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struct pmap_ent {
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const char* msg;
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vaddr_t va;
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paddr_t pa;
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vsize_t sz;
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int prot;
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int cache;
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};
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void ixp12x0_bs_init(bus_space_tag_t, void *);
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void ixp12x0_io_bs_init(bus_space_tag_t, void *);
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void ixp12x0_mem_bs_init(bus_space_tag_t, void *);
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void ixp12x0_pci_init(pci_chipset_tag_t, void *);
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void ixp12x0_pci_dma_init(bus_dma_tag_t, void *);
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void ixp12x0_attach(struct ixp12x0_softc *);
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void ixp12x0_intr_init(void);
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void *ixp12x0_intr_establish(int irq, int ipl, int (*)(void *), void *);
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void ixp12x0_intr_disestablish(void *);
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void ixp12x0_pmap_chunk_table(vaddr_t l1pt, struct pmap_ent* m);
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void ixp12x0_pmap_io_reg(vaddr_t l1pt);
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#endif /* _IXP12X0VAR_H_ */
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