261 lines
7.7 KiB
C
261 lines
7.7 KiB
C
/* $NetBSD: ixp12x0.c,v 1.1 2002/07/15 16:27:16 ichiro Exp $ */
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/*
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* Copyright (c) 2002
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* Ichiro FUKUHARA <ichiro@ichiro.org>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Ichiro FUKUHARA.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <uvm/uvm.h>
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#include <machine/bus.h>
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#include <arm/ixp12x0/ixp12x0reg.h>
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#include <arm/ixp12x0/ixp12x0var.h>
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#include <arm/ixp12x0/ixp12x0_pcireg.h>
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int ixp12x0_pcibus_print(void *, const char *);
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static struct ixp12x0_softc *ixp12x0_softc;
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void
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ixp12x0_attach(sc)
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struct ixp12x0_softc *sc;
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{
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struct pcibus_attach_args pba;
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pcireg_t reg;
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ixp12x0_softc = sc;
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printf("\n");
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/*
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* Subregion for PCI Configuration Spase Registers
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*/
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if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0,
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IXP12X0_PCI_SIZE, &sc->sc_pci_ioh))
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panic("%s: unable to subregion PCI registers\n",
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sc->sc_dev.dv_xname);
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/*
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* PCI bus reset
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*/
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/* assert PCI reset */
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reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh,
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SA_CONTROL) &~ SA_CONTROL_PNR;
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bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
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SA_CONTROL, reg);
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DELAY(10);
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/* XXX Disable door bell and outbound interrupt */
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bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
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PCI_CAP_PTR, 0xc);
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/* Disable door bell int to PCI */
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bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
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DBELL_PCI_MASK, 0xc);
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/* Disable door bell int to SA-core */
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bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
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DBELL_SA_MASK, 0xc);
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bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
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PCI_ADDR_EXT, 0);
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/* Negate PCI reset */
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reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh,
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SA_CONTROL) | SA_CONTROL_PNR;
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bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
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SA_CONTROL, reg);
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DELAY(10);
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/*
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* specify window size of memory access and SDRAM.
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*/
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reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh,
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IXP_PCI_MEM_BAR) | IXP1200_PCI_MEM_BAR;
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bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
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IXP_PCI_MEM_BAR, reg);
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reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh,
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IXP_PCI_IO_BAR) | IXP1200_PCI_IO_BAR;
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bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
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IXP_PCI_IO_BAR, reg);
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reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh,
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IXP_PCI_DRAM_BAR) | IXP1200_PCI_DRAM_BAR;
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bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
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IXP_PCI_DRAM_BAR, reg);
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bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
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CSR_BASE_ADDR_MASK, CSR_BASE_ADDR_MASK_1M);
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bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
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DRAM_BASE_ADDR_MASK, DRAM_BASE_ADDR_MASK_256MB);
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#if DEBUG
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printf("IXP_PCI_MEM_BAR = 0x%08x\nIXP_PCI_IO_BAR = 0x%08x\nIXP_PCI_DRAM_BAR = 0x%08x\nCSR_BASE_ADDR_MASK = 0x%08x\n",
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bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, IXP_PCI_MEM_BAR),
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bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, IXP_PCI_IO_BAR),
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bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, IXP_PCI_DRAM_BAR),
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bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, DRAM_BASE_ADDR_MASK));
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#endif
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/* Initialize complete */
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reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh,
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SA_CONTROL) | 0x1;
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bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
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SA_CONTROL, reg);
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#if DEBUG
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printf("SA_CONTROL = 0x%08x\n",
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bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, SA_CONTROL));
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#endif
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/*
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* Enable bus mastering and I/O,memory access
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*/
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/* host only */
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reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh,
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PCI_COMMAND_STATUS_REG) |
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PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
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PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE;
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bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
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PCI_COMMAND_STATUS_REG, reg);
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#if DEBUG
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printf("PCI_COMMAND_STATUS_REG = 0x%08x\n",
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bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, PCI_COMMAND_STATUS_REG));
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#endif
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/*
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* Initialize the bus space and DMA tags and the PCI chipset tag.
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*/
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ixp12x0_io_bs_init(&sc->ia_pci_iot, sc);
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ixp12x0_mem_bs_init(&sc->ia_pci_memt, sc);
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ixp12x0_pci_init(&sc->ia_pci_chipset, sc);
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ixp12x0_pci_dma_init(&sc->ia_pci_dmat, sc);
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/*
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* Attach the PCI bus.
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*/
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pba.pba_busname = "pci";
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pba.pba_pc = &sc->ia_pci_chipset;
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pba.pba_iot = &sc->ia_pci_iot;
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pba.pba_memt = &sc->ia_pci_memt;
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pba.pba_dmat = &sc->ia_pci_dmat;
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pba.pba_bus = 0; /* bus number = 0 */
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pba.pba_intrswiz = 0; /* XXX */
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pba.pba_intrtag = 0;
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pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED |
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PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY;
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(void) config_found(&sc->sc_dev, &pba, ixp12x0_pcibus_print);
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}
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int
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ixp12x0_pcibus_print(void *aux, const char *pnp)
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{
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struct pcibus_attach_args *pba = aux;
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if (pnp)
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printf("%s at %s", pba->pba_busname, pnp);
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printf(" bus %d", pba->pba_bus);
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return (UNCONF);
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}
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/*
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* IXP12x0 specific I/O registers mapping table
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*/
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static struct pmap_ent map_tbl_ixp12x0[] = {
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{ "StrongARM System and Peripheral Registers",
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IXP12X0_SYS_VBASE, IXP12X0_SYS_HWBASE,
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IXP12X0_SYS_SIZE,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE, },
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{ "PCI Registers Accessible Through StrongARM Core",
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IXP12X0_PCI_VBASE, IXP12X0_PCI_HWBASE,
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IXP12X0_PCI_SIZE,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE, },
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{ "PCI Registers Accessible Through I/O Cycle Access",
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IXP12X0_PCI_IO_VBASE, IXP12X0_PCI_IO_HWBASE,
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IXP12X0_PCI_IO_SIZE,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE, },
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{ "PCI Registers Accessible Through Memory Cycle Access",
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IXP12X0_PCI_MEM_VBASE, IXP12X0_PCI_MEM_VBASE,
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IXP12X0_PCI_MEM_SIZE,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE, },
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{ "PCI Type0 Configuration Space",
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IXP12X0_PCI_TYPE0_VBASE, IXP12X0_PCI_TYPE0_VBASE,
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IXP12X0_PCI_TYPEX_SIZE,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE, },
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{ "PCI Type1 Configuration Space",
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IXP12X0_PCI_TYPE1_VBASE, IXP12X0_PCI_TYPE1_VBASE,
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IXP12X0_PCI_TYPEX_SIZE,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE, },
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{ NULL, 0, 0, 0, 0, 0 },
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};
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/*
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* mapping virtual memories
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*/
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void
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ixp12x0_pmap_chunk_table(vaddr_t l1pt, struct pmap_ent* m)
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{
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int loop;
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loop = 0;
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while (m[loop].msg) {
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printf("mapping %s...\n", m[loop].msg);
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pmap_map_chunk(l1pt, m[loop].va, m[loop].pa,
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m[loop].sz, m[loop].prot, m[loop].cache);
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++loop;
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}
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}
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/*
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* mapping I/O registers
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*/
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void
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ixp12x0_pmap_io_reg(vaddr_t l1pt)
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{
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ixp12x0_pmap_chunk_table(l1pt, map_tbl_ixp12x0);
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}
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void
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ixp12x0_reset(void)
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{
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bus_space_write_4(ixp12x0_softc->sc_iot, ixp12x0_softc->sc_pci_ioh,
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IXPPCI_IXP1200_RESET, RESET_FULL);
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}
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