100 lines
3.2 KiB
C
100 lines
3.2 KiB
C
/* $NetBSD: i82802reg.h,v 1.4 2010/08/23 02:57:19 jakllsch Exp $ */
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/*
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* Copyright (c) 2000 Michael Shalayeff
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Intel 82802AB/82802AC Firmware Hub
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*
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* see: ftp://download.intel.com/design/chipsets/datashts/29065804.pdf
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* and http://www.intel.com/design/chipsets/datashts/29065804.pdf
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*/
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/*
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* MMIO bases and sizes
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*/
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#define I82802AC_REGBASE 0xffb00000
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#define I82802AC_MEMBASE 0xfff00000
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#define I82802AC_WINSIZE 0x00100000
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#define I82802AB_MEMBASE 0xfff80000
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#define I82802AB_WINSIZE 0x00080000
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#define I82802_MFG 0x89
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#define I82802AB_ID 0xad
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#define I82802AC_ID 0xac
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/*
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* Intel FWH registers
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*/
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#define I82802_T_BLOCK_LK 0xf0002
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#define I82802_T_MINUS01_LK 0xe0002
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#define I82802_T_MINUS02_LK 0xd0002
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#define I82802_T_MINUS03_LK 0xc0002
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#define I82802_T_MINUS04_LK 0xb0002
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#define I82802_T_MINUS05_LK 0xa0002
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#define I82802_T_MINUS06_LK 0x90002
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#define I82802_T_MINUS07_LK 0x80002
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#define I82802_T_MINUS08_LK 0x70002
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#define I82802_T_MINUS09_LK 0x60002
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#define I82802_T_MINUS10_LK 0x50002
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#define I82802_T_MINUS11_LK 0x40002
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#define I82802_T_MINUS12_LK 0x30002
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#define I82802_T_MINUS13_LK 0x20002
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#define I82802_T_MINUS14_LK 0x10002
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#define I82802_T_MINUS15_LK 0x00002
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#define I82802_GPI_REG 0xc0100
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#define I82802_RNG_HSR 0xc015f /* Hardware Status */
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#define I82802_RNG_DSR 0xc0160 /* Data Status */
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#define I82802_RNG_DR 0xc0161 /* Data */
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/*
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* T_BLOCK_LK and T_MINUS_* (block locking registers)
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* (table 4-5)
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*/
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#define I82802_BLR_RD 0x04
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#define I82802_BLR_LD 0x02
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#define I82802_BLR_WL 0x01
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/*
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* General Purpose Inputs Register
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* (table 4-7)
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*/ /* PLCC32/TSOP40 pin # */
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#define I82802_GPI_REG_FGPI4 0x10 /* 30 / 7 */
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#define I82802_GPI_REG_FGPI3 0x08 /* 3 / 15 */
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#define I82802_GPI_REG_FGPI2 0x04 /* 4 / 16 */
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#define I82802_GPI_REG_FGPI1 0x02 /* 5 / 17 */
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#define I82802_GPI_REG_FGPI0 0x01 /* 6 / 18 */
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/*
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* RNG registers
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*/
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#define I82802_RNG_HSR_PRESENT 0x40
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#define I82802_RNG_HSR_ENABLE 0x01
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#define I82802_RNG_DSR_VALID 0x01
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