671 lines
16 KiB
C
671 lines
16 KiB
C
/* $NetBSD: mac68k5380.c,v 1.14 1995/10/01 05:10:20 briggs Exp $ */
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/*
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* Copyright (c) 1995 Allen Briggs
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Allen Briggs
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Derived from atari5380.c for the mac68k port of NetBSD.
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*
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <sys/dkstat.h>
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#include <sys/syslog.h>
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#include <sys/buf.h>
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#include <scsi/scsi_all.h>
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#include <scsi/scsi_message.h>
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#include <scsi/scsiconf.h>
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/*
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* Include the driver definitions
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*/
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#include <mac68k/dev/ncr5380reg.h>
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#include <machine/stdarg.h>
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#include "../mac68k/via.h"
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/*
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* Set the various driver options
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*/
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#define NREQ 18 /* Size of issue queue */
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#define AUTO_SENSE 1 /* Automatically issue a request-sense */
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#define DRNAME ncrscsi /* used in various prints */
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#undef DBG_SEL /* Show the selection process */
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#undef DBG_REQ /* Show enqueued/ready requests */
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#undef DBG_NOWRITE /* Do not allow writes to the targets */
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#undef DBG_PIO /* Show the polled-I/O process */
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#undef DBG_INF /* Show information transfer process */
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#define DBG_NOSTATIC /* No static functions, all in DDB trace*/
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#undef DBG_PID /* Keep track of driver */
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#undef REAL_DMA /* Use DMA if sensible */
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#define fair_to_keep_dma() 1
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#define claimed_dma() 1
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#define reconsider_dma()
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#define USE_PDMA 1 /* Use special pdma-transfer function */
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#define MIN_PHYS 0x2000 /* pdma space w/ /DSACK is only 0x2000 */
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#define ENABLE_NCR5380(sc) cur_softc = sc;
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/*
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* softc of currently active controller (well, we only have one for now).
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*/
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static struct ncr_softc *cur_softc;
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struct scsi_5380 {
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volatile u_char scsi_5380[8*16]; /* 8 regs, 1 every 16th byte. */
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};
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extern vm_offset_t SCSIBase;
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static volatile u_char *ncr = (volatile u_char *) 0x10000;
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static volatile u_char *ncr_5380_with_drq = (volatile u_char *) 0x6000;
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static volatile u_char *ncr_5380_without_drq = (volatile u_char *) 0x12000;
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static volatile u_char *scsi_enable = NULL;
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#define SCSI_5380 ((struct scsi_5380 *) ncr)
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#define GET_5380_REG(rnum) SCSI_5380->scsi_5380[((rnum)<<4)]
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#define SET_5380_REG(rnum,val) (SCSI_5380->scsi_5380[((rnum)<<4)] = (val))
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void ncr5380_irq_intr(void *);
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void ncr5380_drq_intr(void *);
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static __inline__ void
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scsi_clr_ipend()
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{
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int tmp;
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tmp = GET_5380_REG(NCR5380_IRCV);
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}
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extern __inline__ void
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scsi_ienable()
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{
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int s;
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s = splhigh();
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*scsi_enable = 0x80 | (V2IF_SCSIIRQ | V2IF_SCSIDRQ);
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splx(s);
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}
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extern __inline__ void
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scsi_idisable()
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{
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int s;
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s = splhigh();
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*scsi_enable = V2IF_SCSIIRQ | V2IF_SCSIDRQ;
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splx(s);
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}
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static void
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scsi_mach_init(sc)
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struct ncr_softc *sc;
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{
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static int initted = 0;
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if (initted++)
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panic("scsi_mach_init called again.\n");
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ncr = (volatile u_char *)
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(SCSIBase + (u_long) ncr);
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ncr_5380_with_drq = (volatile u_char *)
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(SCSIBase + (u_int) ncr_5380_with_drq);
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ncr_5380_without_drq = (volatile u_char *)
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(SCSIBase + (u_int) ncr_5380_without_drq);
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if (VIA2 == VIA2OFF)
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scsi_enable = Via1Base + VIA2 * 0x2000 + vIER;
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else
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scsi_enable = Via1Base + VIA2 * 0x2000 + rIER;
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mac68k_register_scsi_irq(ncr5380_irq_intr, sc);
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mac68k_register_scsi_drq(ncr5380_drq_intr, sc);
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}
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static int
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machine_match(pdp, cdp, auxp, cd)
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struct device *pdp;
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struct cfdata *cdp;
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void *auxp;
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struct cfdriver *cd;
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{
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if (matchbyname(pdp, cdp, auxp) == 0)
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return 0;
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if (!mac68k_machine.scsi80)
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return 0;
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if (cdp->cf_unit != 0)
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return 0;
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return 1;
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}
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#if USE_PDMA
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int pdma_5380_dir = 0;
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u_char *pending_5380_data;
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u_long pending_5380_count;
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/* #define DEBUG 1 Maybe we try with this off eventually. */
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#if DEBUG
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int pdma_5380_sends = 0;
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int pdma_5380_bytes = 0;
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char *pdma_5380_state="";
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void
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pdma_stat()
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{
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printf("PDMA SCSI: %d xfers completed for %d bytes.\n",
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pdma_5380_sends, pdma_5380_bytes);
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printf("pdma_5380_dir = %d.\n",
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pdma_5380_dir);
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printf("datap = 0x%x, remainder = %d.\n",
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pending_5380_data, pending_5380_count);
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printf("pdma_5380_state = %s.\n", pdma_5380_state);
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}
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#endif
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void
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pdma_cleanup(void)
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{
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SC_REQ *reqp = connected;
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int bytes, s;
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s = splbio();
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pdma_5380_dir = 0;
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#if DEBUG
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pdma_5380_state = "in pdma_cleanup().";
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pdma_5380_sends++;
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pdma_5380_bytes+=(reqp->xdata_len - pending_5380_count);
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#endif
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/*
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* Update pointers.
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*/
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reqp->xdata_ptr += reqp->xdata_len - pending_5380_count;
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reqp->xdata_len = pending_5380_count;
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/*
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* Reset DMA mode.
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*/
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SET_5380_REG(NCR5380_MODE, GET_5380_REG(NCR5380_MODE) & ~SC_M_DMA);
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/*
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* Clear any pending interrupts.
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*/
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scsi_clr_ipend();
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/*
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* Tell interrupt functions that DMA has ended.
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*/
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reqp->dr_flag &= ~DRIVER_IN_DMA;
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SET_5380_REG(NCR5380_MODE, IMODE_BASE);
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SET_5380_REG(NCR5380_ICOM, 0);
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splx(s);
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/*
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* Back for more punishment.
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*/
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run_main(cur_softc);
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}
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#endif
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static __inline__ int
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pdma_ready()
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{
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#if USE_PDMA
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SC_REQ *reqp = connected;
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int dmstat, idstat;
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extern u_char ncr5380_no_parchk;
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if (pdma_5380_dir) {
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#if DEBUG
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pdma_5380_state = "got irq interrupt in xfer.";
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#endif
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/*
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* If Mr. IRQ isn't set one might wonder how we got
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* here. It does happen, though.
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*/
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dmstat = GET_5380_REG(NCR5380_DMSTAT);
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if (!(dmstat & SC_IRQ_SET)) {
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return 0;
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}
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/*
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* For a phase mis-match, ATN is a "don't care," IRQ is 1 and
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* all other bits in the Bus & Status Register are 0. Also,
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* the current SCSI Bus Status Register has a 1 for BSY and
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* REQ. Since we're just checking that this interrupt isn't a
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* reselection or a reset, we just check for either.
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*/
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idstat = GET_5380_REG(NCR5380_IDSTAT);
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if ( ((dmstat & (0xff & ~SC_ATN_STAT)) == SC_IRQ_SET)
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&& ((idstat & (SC_S_BSY|SC_S_REQ))
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== (SC_S_BSY | SC_S_REQ)) ) {
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pdma_cleanup();
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return 1;
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} else if (PH_IN(reqp->phase) && (dmstat & SC_PAR_ERR)) {
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if (!(ncr5380_no_parchk & (1 << reqp->targ_id)))
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/* XXX: Should be parity error ???? */
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reqp->xs->error = XS_DRIVER_STUFFUP;
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/* XXX: is this the right reaction? */
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pdma_cleanup();
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return 1;
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} else if ( !(idstat & SC_S_REQ)
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|| (((idstat>>2) & 7) != reqp->phase)) {
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#ifdef DIAGNOSTIC
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/* XXX: is this the right reaction? Can this happen? */
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scsi_show();
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printf("Unexpected phase change.\n");
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#endif
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reqp->xs->error = XS_DRIVER_STUFFUP;
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pdma_cleanup();
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return 1;
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} else {
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scsi_show();
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panic("Spurious interrupt during PDMA xfer.\n");
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}
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}
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#endif
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return 0;
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}
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void
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ncr5380_irq_intr(p)
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void *p;
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{
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struct ncr_softc *sc = p;
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#if USE_PDMA
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if (pdma_ready()) {
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return;
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}
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#endif
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if (GET_5380_REG(NCR5380_DMSTAT) & SC_IRQ_SET) {
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scsi_idisable();
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ncr_ctrl_intr(cur_softc);
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}
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}
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/*
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* This is the meat of the PDMA transfer.
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* When we get here, we shove data as fast as the mac can take it.
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* We depend on several things:
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* * All macs after the Mac Plus that have a 5380 chip should have a general
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* logic IC that handshakes data for blind transfers.
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* * If the SCSI controller finishes sending/receiving data before we do,
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* the same general logic IC will generate a /BERR for us in short order.
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* * The fault address for said /BERR minus the base address for the
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* transfer will be the amount of data that was actually written.
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*
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* We use the nofault flag and the setjmp/longjmp in locore.s so we can
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* detect and handle the bus error for early termination of a command.
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* This is usually caused by a disconnecting target.
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*/
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void
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ncr5380_drq_intr(p)
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void *p;
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{
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#if USE_PDMA
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extern int *nofault, mac68k_buserr_addr;
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struct ncr_softc *sc = p;
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label_t faultbuf;
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register int count;
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volatile u_int32_t *long_drq;
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u_int32_t *long_data;
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volatile u_int8_t *drq;
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u_int8_t *data;
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/*
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* If we're not ready to xfer data, just return.
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*/
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if ( !(GET_5380_REG(NCR5380_DMSTAT) & SC_DMA_REQ)
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|| !pdma_5380_dir)
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return;
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#if DEBUG
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pdma_5380_state = "got drq interrupt.";
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#endif
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/*
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* Setup for a possible bus error caused by SCSI controller
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* switching out of DATA-IN/OUT before we're done with the
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* current transfer.
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*/
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nofault = (int *) &faultbuf;
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if (setjmp((label_t *) nofault)) {
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nofault = (int *) 0;
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#if DEBUG
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pdma_5380_state = "buserr in xfer.";
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#endif
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count = ( (u_long) mac68k_buserr_addr
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- (u_long) ncr_5380_with_drq);
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if ((count < 0) || (count > pending_5380_count)) {
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printf("pdma in: count = %d (0x%x) (pending "
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"count %d)\n", count, count,
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pending_5380_count);
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panic("something is wrong");
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}
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pending_5380_data += count;
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pending_5380_count -= count;
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#if DEBUG
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pdma_5380_state = "handled bus error in xfer.";
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#endif
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mac68k_buserr_addr = 0;
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return;
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}
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if (pdma_5380_dir == 2) { /* Data In */
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int resid;
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/*
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* Get the dest address aligned.
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*/
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resid = count = 4 - (((int) pending_5380_data) & 0x3);
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if (count < 4) {
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data = (u_int8_t *) pending_5380_data;
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drq = (u_int8_t *) ncr_5380_with_drq;
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while (count) {
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#define R1 *data++ = *drq++
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R1; count--;
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#undef R1
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}
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pending_5380_data += resid;
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pending_5380_count -= resid;
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}
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/*
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* Get ready to start the transfer.
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*/
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while (pending_5380_count) {
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int dcount;
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dcount = count = min(pending_5380_count, MIN_PHYS);
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long_drq = (volatile u_int32_t *) ncr_5380_with_drq;
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long_data = (u_int32_t *) pending_5380_data;
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#define R4 *long_data++ = *long_drq++
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while ( count >= 512 ) {
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if (!(GET_5380_REG(NCR5380_DMSTAT) & SC_DMA_REQ)) {
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nofault = (int *) 0;
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pending_5380_data += (dcount - count);
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pending_5380_count -= (dcount - count);
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#if DEBUG
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pdma_5380_state = "drq low";
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#endif
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return;
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}
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R4; R4; R4; R4; R4; R4; R4; R4;
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R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */
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R4; R4; R4; R4; R4; R4; R4; R4;
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R4; R4; R4; R4; R4; R4; R4; R4; /* 128 */
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R4; R4; R4; R4; R4; R4; R4; R4;
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R4; R4; R4; R4; R4; R4; R4; R4;
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R4; R4; R4; R4; R4; R4; R4; R4;
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R4; R4; R4; R4; R4; R4; R4; R4; /* 256 */
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R4; R4; R4; R4; R4; R4; R4; R4;
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R4; R4; R4; R4; R4; R4; R4; R4;
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R4; R4; R4; R4; R4; R4; R4; R4;
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R4; R4; R4; R4; R4; R4; R4; R4;
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R4; R4; R4; R4; R4; R4; R4; R4;
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R4; R4; R4; R4; R4; R4; R4; R4;
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R4; R4; R4; R4; R4; R4; R4; R4;
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R4; R4; R4; R4; R4; R4; R4; R4; /* 512 */
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count -= 512;
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}
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while (count >= 4) {
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R4; count -= 4;
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}
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#undef R4
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data = (u_int8_t *) long_data;
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drq = (u_int8_t *) long_drq;
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while (count) {
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#define R1 *data++ = *drq++
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R1; count--;
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#undef R1
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}
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pending_5380_count -= dcount;
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pending_5380_data += dcount;
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}
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} else {
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int resid;
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/*
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* Get the source address aligned.
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*/
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resid = count = 4 - (((int) pending_5380_data) & 0x3);
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if (count < 4) {
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data = (u_int8_t *) pending_5380_data;
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drq = (u_int8_t *) ncr_5380_with_drq;
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while (count) {
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#define W1 *drq++ = *data++
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W1; count--;
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#undef W1
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}
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pending_5380_data += resid;
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pending_5380_count -= resid;
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}
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/*
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* Get ready to start the transfer.
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*/
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while (pending_5380_count) {
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int dcount;
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dcount = count = min(pending_5380_count, MIN_PHYS);
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long_drq = (volatile u_int32_t *) ncr_5380_with_drq;
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long_data = (u_int32_t *) pending_5380_data;
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#define W4 *long_drq++ = *long_data++
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while ( count >= 64 ) {
|
|
W4; W4; W4; W4; W4; W4; W4; W4;
|
|
W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */
|
|
count -= 64;
|
|
}
|
|
while (count >= 4) {
|
|
W4; count -= 4;
|
|
}
|
|
#undef W4
|
|
data = (u_int8_t *) long_data;
|
|
drq = (u_int8_t *) long_drq;
|
|
while (count) {
|
|
#define W1 *drq++ = *data++
|
|
W1; count--;
|
|
#undef W1
|
|
}
|
|
pending_5380_count -= dcount;
|
|
pending_5380_data += dcount;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* OK. No bus error occurred above. Clear the nofault flag
|
|
* so we no longer short-circuit bus errors.
|
|
*/
|
|
nofault = (int *) 0;
|
|
|
|
#if DEBUG
|
|
pdma_5380_state = "done in xfer--waiting.";
|
|
#endif
|
|
|
|
/*
|
|
* Is this necessary?
|
|
*/
|
|
while (!( (GET_5380_REG(NCR5380_DMSTAT) & SC_ACK_STAT)
|
|
|| (GET_5380_REG(NCR5380_IDSTAT) & SC_S_REQ) ));
|
|
|
|
/*
|
|
* Update pointers for pdma_cleanup().
|
|
*/
|
|
pending_5380_data += pending_5380_count;
|
|
pending_5380_count = 0;
|
|
|
|
#if DEBUG
|
|
pdma_5380_state = "done in xfer.";
|
|
#endif
|
|
|
|
pdma_cleanup();
|
|
return;
|
|
#endif /* if USE_PDMA */
|
|
}
|
|
|
|
#if USE_PDMA
|
|
|
|
#define SCSI_TIMEOUT_VAL 10000000
|
|
|
|
static int
|
|
transfer_pdma(phasep, data, count)
|
|
u_char *phasep;
|
|
u_char *data;
|
|
u_long *count;
|
|
{
|
|
SC_REQ *reqp = connected;
|
|
int len = *count, i, scsi_timeout = SCSI_TIMEOUT_VAL;
|
|
int s, err;
|
|
|
|
if (pdma_5380_dir) {
|
|
panic("ncrscsi: transfer_pdma called when operation already "
|
|
"pending.\n");
|
|
}
|
|
#if DEBUG
|
|
pdma_5380_state = "in transfer_pdma.";
|
|
#endif
|
|
|
|
/*
|
|
* Don't bother with PDMA if we can't sleep or for small transfers.
|
|
*/
|
|
if (reqp->dr_flag & DRIVER_NOINT) {
|
|
#if DEBUG
|
|
pdma_5380_state = "pdma, actually using transfer_pio.";
|
|
#endif
|
|
transfer_pio(phasep, data, count, 0);
|
|
return -1;
|
|
}
|
|
|
|
/*
|
|
* We are probably already at spl2(), so this is likely a no-op.
|
|
* Paranoia.
|
|
*/
|
|
s = splbio();
|
|
|
|
scsi_idisable();
|
|
|
|
/*
|
|
* Match phases with target.
|
|
*/
|
|
SET_5380_REG(NCR5380_TCOM, *phasep);
|
|
|
|
/*
|
|
* Clear pending interrupts.
|
|
*/
|
|
scsi_clr_ipend();
|
|
|
|
/*
|
|
* Wait until target asserts BSY.
|
|
*/
|
|
while ( ((GET_5380_REG(NCR5380_IDSTAT) & SC_S_BSY) == 0)
|
|
&& (--scsi_timeout) );
|
|
if (!scsi_timeout) {
|
|
#if DIAGNOSTIC
|
|
printf("scsi timeout: waiting for BSY in %s.\n",
|
|
(*phasep == PH_DATAOUT) ? "pdma_out" : "pdma_in");
|
|
#endif
|
|
goto scsi_timeout_error;
|
|
}
|
|
|
|
/*
|
|
* Tell the driver that we're in DMA mode.
|
|
*/
|
|
reqp->dr_flag |= DRIVER_IN_DMA;
|
|
|
|
/*
|
|
* Set DMA mode and assert data bus.
|
|
*/
|
|
SET_5380_REG(NCR5380_MODE, GET_5380_REG(NCR5380_MODE) | SC_M_DMA);
|
|
SET_5380_REG(NCR5380_ICOM, GET_5380_REG(NCR5380_ICOM) | SC_ADTB);
|
|
|
|
/*
|
|
* Load transfer values for DRQ interrupt handlers.
|
|
*/
|
|
pending_5380_data = data;
|
|
pending_5380_count = len;
|
|
|
|
#if DEBUG
|
|
pdma_5380_state = "wait for interrupt.";
|
|
#endif
|
|
|
|
/*
|
|
* Set the transfer function to be called on DRQ interrupts.
|
|
* And note that we're waiting.
|
|
*/
|
|
switch (*phasep) {
|
|
default:
|
|
panic("Unexpected phase in transfer_pdma.\n");
|
|
case PH_DATAOUT:
|
|
pdma_5380_dir = 1;
|
|
SET_5380_REG(NCR5380_DMSTAT, 0);
|
|
break;
|
|
case PH_DATAIN:
|
|
pdma_5380_dir = 2;
|
|
SET_5380_REG(NCR5380_IRCV, 0);
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* Now that we're set up, enable interrupts and drop processor
|
|
* priority back down.
|
|
*/
|
|
scsi_ienable();
|
|
splx(s);
|
|
return 0;
|
|
|
|
scsi_timeout_error:
|
|
/*
|
|
* Clear the DMA mode.
|
|
*/
|
|
SET_5380_REG(NCR5380_MODE, GET_5380_REG(NCR5380_MODE) & ~SC_M_DMA);
|
|
return -1;
|
|
}
|
|
#endif /* if USE_PDMA */
|
|
|
|
/* Include general routines. */
|
|
#include <mac68k/dev/ncr5380.c>
|