1529 lines
34 KiB
C
1529 lines
34 KiB
C
/* $NetBSD: scif.c,v 1.33 2002/10/23 09:11:56 jdolecek Exp $ */
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/*-
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* Copyright (C) 1999 T.Horiuchi and SAITOH Masanobu. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*-
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* Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Charles M. Hannum.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)com.c 7.5 (Berkeley) 5/16/91
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*/
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/*
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* SH internal serial driver
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*
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* This code is derived from both z8530tty.c and com.c
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*/
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#include "opt_kgdb.h"
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#include "opt_scif.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/tty.h>
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#include <sys/proc.h>
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#include <sys/conf.h>
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#include <sys/file.h>
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#include <sys/syslog.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <sys/kgdb.h>
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#include <dev/cons.h>
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#include <sh3/clock.h>
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#include <sh3/exception.h>
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#include <sh3/scifreg.h>
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#include <machine/intr.h>
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#include <sh3/dev/scifvar.h>
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#include "locators.h"
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static void scifstart(struct tty *);
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static int scifparam(struct tty *, struct termios *);
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static int kgdb_attached;
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void scifcnprobe(struct consdev *);
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void scifcninit(struct consdev *);
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void scifcnputc(dev_t, int);
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int scifcngetc(dev_t);
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void scifcnpoolc(dev_t, int);
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void scif_intr_init(void);
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int scifintr(void *);
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struct scif_softc {
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struct device sc_dev; /* boilerplate */
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struct tty *sc_tty;
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void *sc_si;
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struct callout sc_diag_ch;
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#if 0
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bus_space_tag_t sc_iot; /* ISA i/o space identifier */
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bus_space_handle_t sc_ioh; /* ISA io handle */
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int sc_drq;
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int sc_frequency;
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#endif
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u_int sc_overflows,
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sc_floods,
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sc_errors; /* number of retries so far */
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u_char sc_status[7]; /* copy of registers */
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int sc_hwflags;
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int sc_swflags;
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u_int sc_fifolen;
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u_int sc_r_hiwat,
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sc_r_lowat;
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u_char *volatile sc_rbget,
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*volatile sc_rbput;
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volatile u_int sc_rbavail;
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u_char *sc_rbuf,
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*sc_ebuf;
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u_char *sc_tba; /* transmit buffer address */
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u_int sc_tbc, /* transmit byte count */
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sc_heldtbc;
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volatile u_char sc_rx_flags,
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#define RX_TTY_BLOCKED 0x01
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#define RX_TTY_OVERFLOWED 0x02
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#define RX_IBUF_BLOCKED 0x04
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#define RX_IBUF_OVERFLOWED 0x08
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#define RX_ANY_BLOCK 0x0f
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sc_tx_busy, /* working on an output chunk */
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sc_tx_done, /* done with one output chunk */
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sc_tx_stopped, /* H/W level stop (lost CTS) */
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sc_st_check, /* got a status interrupt */
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sc_rx_ready;
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volatile u_char sc_heldchange;
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};
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/* controller driver configuration */
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static int scif_match(struct device *, struct cfdata *, void *);
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static void scif_attach(struct device *, struct device *, void *);
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void scif_break(struct scif_softc *, int);
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void scif_iflush(struct scif_softc *);
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#define integrate static inline
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#ifdef __HAVE_GENERIC_SOFT_INTERRUPTS
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void scifsoft(void *);
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#else
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#ifndef __NO_SOFT_SERIAL_INTERRUPT
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void scifsoft(void);
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#else
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void scifsoft(void *);
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#endif
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#endif
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integrate void scif_rxsoft(struct scif_softc *, struct tty *);
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integrate void scif_txsoft(struct scif_softc *, struct tty *);
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integrate void scif_stsoft(struct scif_softc *, struct tty *);
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integrate void scif_schedrx(struct scif_softc *);
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void scifdiag(void *);
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#define SCIFUNIT_MASK 0x7ffff
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#define SCIFDIALOUT_MASK 0x80000
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#define SCIFUNIT(x) (minor(x) & SCIFUNIT_MASK)
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#define SCIFDIALOUT(x) (minor(x) & SCIFDIALOUT_MASK)
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/* Macros to clear/set/test flags. */
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#define SET(t, f) (t) |= (f)
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#define CLR(t, f) (t) &= ~(f)
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#define ISSET(t, f) ((t) & (f))
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/* Hardware flag masks */
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#define SCIF_HW_NOIEN 0x01
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#define SCIF_HW_FIFO 0x02
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#define SCIF_HW_FLOW 0x08
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#define SCIF_HW_DEV_OK 0x20
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#define SCIF_HW_CONSOLE 0x40
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#define SCIF_HW_KGDB 0x80
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/* Buffer size for character buffer */
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#define SCIF_RING_SIZE 2048
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/* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */
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u_int scif_rbuf_hiwat = (SCIF_RING_SIZE * 1) / 4;
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u_int scif_rbuf_lowat = (SCIF_RING_SIZE * 3) / 4;
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#define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */
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int scifconscflag = CONMODE;
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int scifisconsole = 0;
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#ifdef SCIFCN_SPEED
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unsigned int scifcn_speed = SCIFCN_SPEED;
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#else
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unsigned int scifcn_speed = 9600;
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#endif
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#define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */
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#ifndef __HAVE_GENERIC_SOFT_INTERRUPTS
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#ifdef __NO_SOFT_SERIAL_INTERRUPT
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volatile int scif_softintr_scheduled;
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struct callout scif_soft_ch = CALLOUT_INITIALIZER;
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#endif
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#endif
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u_int scif_rbuf_size = SCIF_RING_SIZE;
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CFATTACH_DECL(scif, sizeof(struct scif_softc),
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scif_match, scif_attach, NULL, NULL);
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extern struct cfdriver scif_cd;
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dev_type_open(scifopen);
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dev_type_close(scifclose);
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dev_type_read(scifread);
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dev_type_write(scifwrite);
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dev_type_ioctl(scifioctl);
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dev_type_stop(scifstop);
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dev_type_tty(sciftty);
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dev_type_poll(scifpoll);
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const struct cdevsw scif_cdevsw = {
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scifopen, scifclose, scifread, scifwrite, scifioctl,
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scifstop, sciftty, scifpoll, nommap, ttykqfilter, D_TTY
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};
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void InitializeScif (unsigned int);
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/*
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* following functions are debugging prupose only
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*/
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#define CR 0x0D
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#define USART_ON (unsigned int)~0x08
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void scif_putc(unsigned char);
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unsigned char scif_getc(void);
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int ScifErrCheck(void);
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/*
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* InitializeScif
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* : unsigned int bps;
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* : SCIF(Serial Communication Interface)
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*/
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void
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InitializeScif(unsigned int bps)
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{
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/* Initialize SCR */
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SHREG_SCSCR2 = 0x00;
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#if 0
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SHREG_SCFCR2 = SCFCR2_TFRST | SCFCR2_RFRST | SCFCR2_MCE;
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#else
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SHREG_SCFCR2 = SCFCR2_TFRST | SCFCR2_RFRST;
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#endif
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/* Serial Mode Register */
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SHREG_SCSMR2 = 0x00; /* 8bit,NonParity,Even,1Stop */
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/* Bit Rate Register */
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SHREG_SCBRR2 = divrnd(sh_clock_get_pclock(), 32 * bps) - 1;
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/*
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* wait 1mSec, because Send/Recv must begin 1 bit period after
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* BRR is set.
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*/
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delay(1000);
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#if 0
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SHREG_SCFCR2 = FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1 | SCFCR2_MCE;
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#else
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SHREG_SCFCR2 = FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1;
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#endif
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/* Send permission, Receive permission ON */
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SHREG_SCSCR2 = SCSCR2_TE | SCSCR2_RE;
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/* Serial Status Register */
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SHREG_SCSSR2 &= SCSSR2_TDFE; /* Clear Status */
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}
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/*
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* scif_putc
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* : unsigned char c;
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*/
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void
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scif_putc(unsigned char c)
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{
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/* wait for ready */
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while ((SHREG_SCFDR2 & SCFDR2_TXCNT) == SCFDR2_TXF_FULL)
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;
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/* write send data to send register */
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SHREG_SCFTDR2 = c;
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/* clear ready flag */
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SHREG_SCSSR2 &= ~(SCSSR2_TDFE | SCSSR2_TEND);
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}
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/*
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* : ScifErrCheck
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* 0x80 = error
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* 0x08 = frame error
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* 0x04 = parity error
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*/
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int
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ScifErrCheck(void)
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{
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return(SHREG_SCSSR2 & (SCSSR2_ER | SCSSR2_FER | SCSSR2_PER));
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}
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/*
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* scif_getc
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*/
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unsigned char
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scif_getc(void)
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{
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unsigned char c, err_c;
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#ifdef SH4
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unsigned short err_c2;
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#endif
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while (1) {
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/* wait for ready */
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while ((SHREG_SCFDR2 & SCFDR2_RECVCNT) == 0)
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;
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c = SHREG_SCFRDR2;
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err_c = SHREG_SCSSR2;
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SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_RDF
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| SCSSR2_DR);
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#ifdef SH4
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if (CPU_IS_SH4) {
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err_c2 = SHREG_SCLSR2;
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SHREG_SCLSR2 &= ~SCLSR2_ORER;
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}
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#endif
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if ((err_c & (SCSSR2_ER | SCSSR2_BRK | SCSSR2_FER
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| SCSSR2_PER)) == 0) {
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#ifdef SH4
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if (CPU_IS_SH4 && ((err_c2 & SCLSR2_ORER) == 0))
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#endif
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return(c);
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}
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}
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}
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#if 0
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#define SCIF_MAX_UNITS 2
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#else
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#define SCIF_MAX_UNITS 1
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#endif
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static int
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scif_match(struct device *parent, struct cfdata *cfp, void *aux)
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{
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if (strcmp(cfp->cf_name, "scif")
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|| cfp->cf_unit >= SCIF_MAX_UNITS)
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return 0;
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return 1;
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}
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static void
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scif_attach(struct device *parent, struct device *self, void *aux)
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{
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struct scif_softc *sc = (struct scif_softc *)self;
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struct tty *tp;
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sc->sc_hwflags = 0; /* XXX */
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sc->sc_swflags = 0; /* XXX */
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sc->sc_fifolen = 16;
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if (scifisconsole || kgdb_attached) {
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/* InitializeScif(scifcn_speed); */
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SET(sc->sc_hwflags, SCIF_HW_CONSOLE);
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SET(sc->sc_swflags, TIOCFLAG_SOFTCAR);
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if (kgdb_attached) {
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SET(sc->sc_hwflags, SCIF_HW_KGDB);
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printf("\n%s: kgdb\n", sc->sc_dev.dv_xname);
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} else {
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printf("\n%s: console\n", sc->sc_dev.dv_xname);
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}
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} else {
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InitializeScif(9600);
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printf("\n");
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}
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callout_init(&sc->sc_diag_ch);
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#ifdef SH4
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intc_intr_establish(SH4_INTEVT_SCIF_ERI, IST_LEVEL, IPL_SERIAL,
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scifintr, sc);
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intc_intr_establish(SH4_INTEVT_SCIF_RXI, IST_LEVEL, IPL_SERIAL,
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scifintr, sc);
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intc_intr_establish(SH4_INTEVT_SCIF_BRI, IST_LEVEL, IPL_SERIAL,
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scifintr, sc);
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intc_intr_establish(SH4_INTEVT_SCIF_TXI, IST_LEVEL, IPL_SERIAL,
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scifintr, sc);
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#else
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intc_intr_establish(SH7709_INTEVT2_SCIF_ERI, IST_LEVEL, IPL_SERIAL,
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scifintr, sc);
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intc_intr_establish(SH7709_INTEVT2_SCIF_RXI, IST_LEVEL, IPL_SERIAL,
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scifintr, sc);
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intc_intr_establish(SH7709_INTEVT2_SCIF_BRI, IST_LEVEL, IPL_SERIAL,
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scifintr, sc);
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intc_intr_establish(SH7709_INTEVT2_SCIF_TXI, IST_LEVEL, IPL_SERIAL,
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scifintr, sc);
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#endif
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#ifdef __HAVE_GENERIC_SOFT_INTERRUPTS
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sc->sc_si = softintr_establish(IPL_SOFTSERIAL, scifsoft, sc);
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#endif
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SET(sc->sc_hwflags, SCIF_HW_DEV_OK);
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tp = ttymalloc();
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tp->t_oproc = scifstart;
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tp->t_param = scifparam;
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tp->t_hwiflow = NULL;
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sc->sc_tty = tp;
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sc->sc_rbuf = malloc(scif_rbuf_size << 1, M_DEVBUF, M_NOWAIT);
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if (sc->sc_rbuf == NULL) {
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printf("%s: unable to allocate ring buffer\n",
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sc->sc_dev.dv_xname);
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return;
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}
|
|
sc->sc_ebuf = sc->sc_rbuf + (scif_rbuf_size << 1);
|
|
|
|
tty_attach(tp);
|
|
}
|
|
|
|
/*
|
|
* Start or restart transmission.
|
|
*/
|
|
static void
|
|
scifstart(struct tty *tp)
|
|
{
|
|
struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)];
|
|
int s;
|
|
|
|
s = spltty();
|
|
if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP))
|
|
goto out;
|
|
if (sc->sc_tx_stopped)
|
|
goto out;
|
|
|
|
if (tp->t_outq.c_cc <= tp->t_lowat) {
|
|
if (ISSET(tp->t_state, TS_ASLEEP)) {
|
|
CLR(tp->t_state, TS_ASLEEP);
|
|
wakeup(&tp->t_outq);
|
|
}
|
|
selwakeup(&tp->t_wsel);
|
|
if (tp->t_outq.c_cc == 0)
|
|
goto out;
|
|
}
|
|
|
|
/* Grab the first contiguous region of buffer space. */
|
|
{
|
|
u_char *tba;
|
|
int tbc;
|
|
|
|
tba = tp->t_outq.c_cf;
|
|
tbc = ndqb(&tp->t_outq, 0);
|
|
|
|
(void)splserial();
|
|
|
|
sc->sc_tba = tba;
|
|
sc->sc_tbc = tbc;
|
|
}
|
|
|
|
SET(tp->t_state, TS_BUSY);
|
|
sc->sc_tx_busy = 1;
|
|
|
|
/* Enable transmit completion interrupts if necessary. */
|
|
SHREG_SCSCR2 |= SCSCR2_TIE | SCSCR2_RIE;
|
|
|
|
/* Output the first chunk of the contiguous buffer. */
|
|
{
|
|
int n;
|
|
int max;
|
|
int i;
|
|
|
|
n = sc->sc_tbc;
|
|
max = sc->sc_fifolen - ((SHREG_SCFDR2 & SCFDR2_TXCNT) >> 8);
|
|
if (n > max)
|
|
n = max;
|
|
|
|
for (i = 0; i < n; i++) {
|
|
scif_putc(*(sc->sc_tba));
|
|
sc->sc_tba++;
|
|
}
|
|
sc->sc_tbc -= n;
|
|
}
|
|
out:
|
|
splx(s);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Set SCIF tty parameters from termios.
|
|
* XXX - Should just copy the whole termios after
|
|
* making sure all the changes could be done.
|
|
*/
|
|
static int
|
|
scifparam(struct tty *tp, struct termios *t)
|
|
{
|
|
struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)];
|
|
int ospeed = t->c_ospeed;
|
|
int s;
|
|
|
|
if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0)
|
|
return (EIO);
|
|
|
|
/* Check requested parameters. */
|
|
if (ospeed < 0)
|
|
return (EINVAL);
|
|
if (t->c_ispeed && t->c_ispeed != t->c_ospeed)
|
|
return (EINVAL);
|
|
|
|
/*
|
|
* For the console, always force CLOCAL and !HUPCL, so that the port
|
|
* is always active.
|
|
*/
|
|
if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) ||
|
|
ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) {
|
|
SET(t->c_cflag, CLOCAL);
|
|
CLR(t->c_cflag, HUPCL);
|
|
}
|
|
|
|
/*
|
|
* If there were no changes, don't do anything. This avoids dropping
|
|
* input and improves performance when all we did was frob things like
|
|
* VMIN and VTIME.
|
|
*/
|
|
if (tp->t_ospeed == t->c_ospeed &&
|
|
tp->t_cflag == t->c_cflag)
|
|
return (0);
|
|
|
|
#if 0
|
|
/* XXX (msaitoh) */
|
|
lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag);
|
|
#endif
|
|
|
|
s = splserial();
|
|
|
|
/*
|
|
* Set the flow control pins depending on the current flow control
|
|
* mode.
|
|
*/
|
|
if (ISSET(t->c_cflag, CRTSCTS)) {
|
|
SHREG_SCFCR2 |= SCFCR2_MCE;
|
|
} else {
|
|
SHREG_SCFCR2 &= ~SCFCR2_MCE;
|
|
}
|
|
|
|
SHREG_SCBRR2 = divrnd(sh_clock_get_pclock(), 32 * ospeed) -1;
|
|
|
|
/*
|
|
* Set the FIFO threshold based on the receive speed.
|
|
*
|
|
* * If it's a low speed, it's probably a mouse or some other
|
|
* interactive device, so set the threshold low.
|
|
* * If it's a high speed, trim the trigger level down to prevent
|
|
* overflows.
|
|
* * Otherwise set it a bit higher.
|
|
*/
|
|
#if 0
|
|
/* XXX (msaitoh) */
|
|
if (ISSET(sc->sc_hwflags, SCIF_HW_HAYESP))
|
|
sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8;
|
|
else if (ISSET(sc->sc_hwflags, SCIF_HW_FIFO))
|
|
sc->sc_fifo = FIFO_ENABLE |
|
|
(t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 :
|
|
t->c_ospeed <= 38400 ? FIFO_TRIGGER_8 : FIFO_TRIGGER_4);
|
|
else
|
|
sc->sc_fifo = 0;
|
|
#endif
|
|
|
|
/* And copy to tty. */
|
|
tp->t_ispeed = 0;
|
|
tp->t_ospeed = t->c_ospeed;
|
|
tp->t_cflag = t->c_cflag;
|
|
|
|
if (!sc->sc_heldchange) {
|
|
if (sc->sc_tx_busy) {
|
|
sc->sc_heldtbc = sc->sc_tbc;
|
|
sc->sc_tbc = 0;
|
|
sc->sc_heldchange = 1;
|
|
}
|
|
#if 0
|
|
/* XXX (msaitoh) */
|
|
else
|
|
scif_loadchannelregs(sc);
|
|
#endif
|
|
}
|
|
|
|
if (!ISSET(t->c_cflag, CHWFLOW)) {
|
|
/* Disable the high water mark. */
|
|
sc->sc_r_hiwat = 0;
|
|
sc->sc_r_lowat = 0;
|
|
if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) {
|
|
CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED);
|
|
scif_schedrx(sc);
|
|
}
|
|
} else {
|
|
sc->sc_r_hiwat = scif_rbuf_hiwat;
|
|
sc->sc_r_lowat = scif_rbuf_lowat;
|
|
}
|
|
|
|
splx(s);
|
|
|
|
#ifdef SCIF_DEBUG
|
|
if (scif_debug)
|
|
scifstatus(sc, "scifparam ");
|
|
#endif
|
|
|
|
if (!ISSET(t->c_cflag, CHWFLOW)) {
|
|
if (sc->sc_tx_stopped) {
|
|
sc->sc_tx_stopped = 0;
|
|
scifstart(tp);
|
|
}
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
void
|
|
scif_iflush(struct scif_softc *sc)
|
|
{
|
|
int i;
|
|
unsigned char c;
|
|
|
|
i = SHREG_SCFDR2 & SCFDR2_RECVCNT;
|
|
|
|
while (i > 0) {
|
|
c = SHREG_SCFRDR2;
|
|
SHREG_SCSSR2 &= ~(SCSSR2_RDF | SCSSR2_DR);
|
|
i--;
|
|
}
|
|
}
|
|
|
|
int
|
|
scifopen(dev_t dev, int flag, int mode, struct proc *p)
|
|
{
|
|
int unit = SCIFUNIT(dev);
|
|
struct scif_softc *sc;
|
|
struct tty *tp;
|
|
int s, s2;
|
|
int error;
|
|
|
|
if (unit >= scif_cd.cd_ndevs)
|
|
return (ENXIO);
|
|
sc = scif_cd.cd_devs[unit];
|
|
if (sc == 0 || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK) ||
|
|
sc->sc_rbuf == NULL)
|
|
return (ENXIO);
|
|
|
|
if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0)
|
|
return (ENXIO);
|
|
|
|
#ifdef KGDB
|
|
/*
|
|
* If this is the kgdb port, no other use is permitted.
|
|
*/
|
|
if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB))
|
|
return (EBUSY);
|
|
#endif /* KGDB */
|
|
|
|
tp = sc->sc_tty;
|
|
|
|
if (ISSET(tp->t_state, TS_ISOPEN) &&
|
|
ISSET(tp->t_state, TS_XCLUDE) &&
|
|
p->p_ucred->cr_uid != 0)
|
|
return (EBUSY);
|
|
|
|
s = spltty();
|
|
|
|
/*
|
|
* Do the following iff this is a first open.
|
|
*/
|
|
if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
|
|
struct termios t;
|
|
|
|
tp->t_dev = dev;
|
|
|
|
s2 = splserial();
|
|
|
|
/* Turn on interrupts. */
|
|
SHREG_SCSCR2 |= SCSCR2_TIE | SCSCR2_RIE;
|
|
|
|
splx(s2);
|
|
|
|
/*
|
|
* Initialize the termios status to the defaults. Add in the
|
|
* sticky bits from TIOCSFLAGS.
|
|
*/
|
|
t.c_ispeed = 0;
|
|
if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) {
|
|
t.c_ospeed = scifcn_speed; /* XXX (msaitoh) */
|
|
t.c_cflag = scifconscflag;
|
|
} else {
|
|
t.c_ospeed = TTYDEF_SPEED;
|
|
t.c_cflag = TTYDEF_CFLAG;
|
|
}
|
|
if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL))
|
|
SET(t.c_cflag, CLOCAL);
|
|
if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS))
|
|
SET(t.c_cflag, CRTSCTS);
|
|
if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF))
|
|
SET(t.c_cflag, MDMBUF);
|
|
/* Make sure scifparam() will do something. */
|
|
tp->t_ospeed = 0;
|
|
(void) scifparam(tp, &t);
|
|
tp->t_iflag = TTYDEF_IFLAG;
|
|
tp->t_oflag = TTYDEF_OFLAG;
|
|
tp->t_lflag = TTYDEF_LFLAG;
|
|
ttychars(tp);
|
|
ttsetwater(tp);
|
|
|
|
s2 = splserial();
|
|
|
|
/* Clear the input ring, and unblock. */
|
|
sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf;
|
|
sc->sc_rbavail = scif_rbuf_size;
|
|
scif_iflush(sc);
|
|
CLR(sc->sc_rx_flags, RX_ANY_BLOCK);
|
|
#if 0
|
|
/* XXX (msaitoh) */
|
|
scif_hwiflow(sc);
|
|
#endif
|
|
|
|
#ifdef SCIF_DEBUG
|
|
if (scif_debug)
|
|
scifstatus(sc, "scifopen ");
|
|
#endif
|
|
|
|
splx(s2);
|
|
}
|
|
|
|
splx(s);
|
|
|
|
error = ttyopen(tp, SCIFDIALOUT(dev), ISSET(flag, O_NONBLOCK));
|
|
if (error)
|
|
goto bad;
|
|
|
|
error = (*tp->t_linesw->l_open)(dev, tp);
|
|
if (error)
|
|
goto bad;
|
|
|
|
return (0);
|
|
|
|
bad:
|
|
|
|
return (error);
|
|
}
|
|
|
|
int
|
|
scifclose(dev_t dev, int flag, int mode, struct proc *p)
|
|
{
|
|
struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)];
|
|
struct tty *tp = sc->sc_tty;
|
|
|
|
/* XXX This is for cons.c. */
|
|
if (!ISSET(tp->t_state, TS_ISOPEN))
|
|
return (0);
|
|
|
|
(*tp->t_linesw->l_close)(tp, flag);
|
|
ttyclose(tp);
|
|
|
|
if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0)
|
|
return (0);
|
|
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
scifread(dev_t dev, struct uio *uio, int flag)
|
|
{
|
|
struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)];
|
|
struct tty *tp = sc->sc_tty;
|
|
|
|
return ((*tp->t_linesw->l_read)(tp, uio, flag));
|
|
}
|
|
|
|
int
|
|
scifwrite(dev_t dev, struct uio *uio, int flag)
|
|
{
|
|
struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)];
|
|
struct tty *tp = sc->sc_tty;
|
|
|
|
return ((*tp->t_linesw->l_write)(tp, uio, flag));
|
|
}
|
|
|
|
int
|
|
scifpoll(dev_t dev, int events, struct proc *p)
|
|
{
|
|
struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)];
|
|
struct tty *tp = sc->sc_tty;
|
|
|
|
return ((*tp->t_linesw->l_poll)(tp, events, p));
|
|
}
|
|
|
|
struct tty *
|
|
sciftty(dev_t dev)
|
|
{
|
|
struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)];
|
|
struct tty *tp = sc->sc_tty;
|
|
|
|
return (tp);
|
|
}
|
|
|
|
int
|
|
scifioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p)
|
|
{
|
|
struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)];
|
|
struct tty *tp = sc->sc_tty;
|
|
int error;
|
|
int s;
|
|
|
|
if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0)
|
|
return (EIO);
|
|
|
|
error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p);
|
|
if (error != EPASSTHROUGH)
|
|
return (error);
|
|
|
|
error = ttioctl(tp, cmd, data, flag, p);
|
|
if (error != EPASSTHROUGH)
|
|
return (error);
|
|
|
|
error = 0;
|
|
|
|
s = splserial();
|
|
|
|
switch (cmd) {
|
|
case TIOCSBRK:
|
|
scif_break(sc, 1);
|
|
break;
|
|
|
|
case TIOCCBRK:
|
|
scif_break(sc, 0);
|
|
break;
|
|
|
|
case TIOCGFLAGS:
|
|
*(int *)data = sc->sc_swflags;
|
|
break;
|
|
|
|
case TIOCSFLAGS:
|
|
error = suser(p->p_ucred, &p->p_acflag);
|
|
if (error)
|
|
break;
|
|
sc->sc_swflags = *(int *)data;
|
|
break;
|
|
|
|
default:
|
|
error = EPASSTHROUGH;
|
|
break;
|
|
}
|
|
|
|
splx(s);
|
|
|
|
return (error);
|
|
}
|
|
|
|
integrate void
|
|
scif_schedrx(struct scif_softc *sc)
|
|
{
|
|
|
|
sc->sc_rx_ready = 1;
|
|
|
|
/* Wake up the poller. */
|
|
#ifdef __HAVE_GENERIC_SOFT_INTERRUPTS
|
|
softintr_schedule(sc->sc_si);
|
|
#else
|
|
#ifndef __NO_SOFT_SERIAL_INTERRUPT
|
|
setsoftserial();
|
|
#else
|
|
if (!scif_softintr_scheduled) {
|
|
scif_softintr_scheduled = 1;
|
|
callout_reset(&scif_soft_ch, 1, scifsoft, NULL);
|
|
}
|
|
#endif
|
|
#endif
|
|
}
|
|
|
|
void
|
|
scif_break(struct scif_softc *sc, int onoff)
|
|
{
|
|
|
|
if (onoff)
|
|
SHREG_SCSSR2 &= ~SCSSR2_TDFE;
|
|
else
|
|
SHREG_SCSSR2 |= SCSSR2_TDFE;
|
|
|
|
#if 0 /* XXX */
|
|
if (!sc->sc_heldchange) {
|
|
if (sc->sc_tx_busy) {
|
|
sc->sc_heldtbc = sc->sc_tbc;
|
|
sc->sc_tbc = 0;
|
|
sc->sc_heldchange = 1;
|
|
} else
|
|
scif_loadchannelregs(sc);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* Stop output, e.g., for ^S or output flush.
|
|
*/
|
|
void
|
|
scifstop(struct tty *tp, int flag)
|
|
{
|
|
struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)];
|
|
int s;
|
|
|
|
s = splserial();
|
|
if (ISSET(tp->t_state, TS_BUSY)) {
|
|
/* Stop transmitting at the next chunk. */
|
|
sc->sc_tbc = 0;
|
|
sc->sc_heldtbc = 0;
|
|
if (!ISSET(tp->t_state, TS_TTSTOP))
|
|
SET(tp->t_state, TS_FLUSH);
|
|
}
|
|
splx(s);
|
|
}
|
|
|
|
void
|
|
scif_intr_init()
|
|
{
|
|
/* XXX */
|
|
}
|
|
|
|
void
|
|
scifdiag(void *arg)
|
|
{
|
|
struct scif_softc *sc = arg;
|
|
int overflows, floods;
|
|
int s;
|
|
|
|
s = splserial();
|
|
overflows = sc->sc_overflows;
|
|
sc->sc_overflows = 0;
|
|
floods = sc->sc_floods;
|
|
sc->sc_floods = 0;
|
|
sc->sc_errors = 0;
|
|
splx(s);
|
|
|
|
log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n",
|
|
sc->sc_dev.dv_xname,
|
|
overflows, overflows == 1 ? "" : "s",
|
|
floods, floods == 1 ? "" : "s");
|
|
}
|
|
|
|
integrate void
|
|
scif_rxsoft(struct scif_softc *sc, struct tty *tp)
|
|
{
|
|
int (*rint)(int c, struct tty *tp) = tp->t_linesw->l_rint;
|
|
u_char *get, *end;
|
|
u_int cc, scc;
|
|
u_char ssr2;
|
|
int code;
|
|
int s;
|
|
|
|
end = sc->sc_ebuf;
|
|
get = sc->sc_rbget;
|
|
scc = cc = scif_rbuf_size - sc->sc_rbavail;
|
|
|
|
if (cc == scif_rbuf_size) {
|
|
sc->sc_floods++;
|
|
if (sc->sc_errors++ == 0)
|
|
callout_reset(&sc->sc_diag_ch, 60 * hz, scifdiag, sc);
|
|
}
|
|
|
|
while (cc) {
|
|
code = get[0];
|
|
ssr2 = get[1];
|
|
if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER | SCSSR2_PER)) {
|
|
if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER))
|
|
SET(code, TTY_FE);
|
|
if (ISSET(ssr2, SCSSR2_PER))
|
|
SET(code, TTY_PE);
|
|
}
|
|
if ((*rint)(code, tp) == -1) {
|
|
/*
|
|
* The line discipline's buffer is out of space.
|
|
*/
|
|
if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) {
|
|
/*
|
|
* We're either not using flow control, or the
|
|
* line discipline didn't tell us to block for
|
|
* some reason. Either way, we have no way to
|
|
* know when there's more space available, so
|
|
* just drop the rest of the data.
|
|
*/
|
|
get += cc << 1;
|
|
if (get >= end)
|
|
get -= scif_rbuf_size << 1;
|
|
cc = 0;
|
|
} else {
|
|
/*
|
|
* Don't schedule any more receive processing
|
|
* until the line discipline tells us there's
|
|
* space available (through scifhwiflow()).
|
|
* Leave the rest of the data in the input
|
|
* buffer.
|
|
*/
|
|
SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED);
|
|
}
|
|
break;
|
|
}
|
|
get += 2;
|
|
if (get >= end)
|
|
get = sc->sc_rbuf;
|
|
cc--;
|
|
}
|
|
|
|
if (cc != scc) {
|
|
sc->sc_rbget = get;
|
|
s = splserial();
|
|
cc = sc->sc_rbavail += scc - cc;
|
|
/* Buffers should be ok again, release possible block. */
|
|
if (cc >= sc->sc_r_lowat) {
|
|
if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) {
|
|
CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED);
|
|
SHREG_SCSCR2 |= SCSCR2_RIE;
|
|
}
|
|
#if 0
|
|
if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) {
|
|
CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED);
|
|
scif_hwiflow(sc);
|
|
}
|
|
#endif
|
|
}
|
|
splx(s);
|
|
}
|
|
}
|
|
|
|
integrate void
|
|
scif_txsoft(struct scif_softc *sc, struct tty *tp)
|
|
{
|
|
|
|
CLR(tp->t_state, TS_BUSY);
|
|
if (ISSET(tp->t_state, TS_FLUSH))
|
|
CLR(tp->t_state, TS_FLUSH);
|
|
else
|
|
ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf));
|
|
(*tp->t_linesw->l_start)(tp);
|
|
}
|
|
|
|
integrate void
|
|
scif_stsoft(struct scif_softc *sc, struct tty *tp)
|
|
{
|
|
#if 0
|
|
/* XXX (msaitoh) */
|
|
u_char msr, delta;
|
|
int s;
|
|
|
|
s = splserial();
|
|
msr = sc->sc_msr;
|
|
delta = sc->sc_msr_delta;
|
|
sc->sc_msr_delta = 0;
|
|
splx(s);
|
|
|
|
if (ISSET(delta, sc->sc_msr_dcd)) {
|
|
/*
|
|
* Inform the tty layer that carrier detect changed.
|
|
*/
|
|
(void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD));
|
|
}
|
|
|
|
if (ISSET(delta, sc->sc_msr_cts)) {
|
|
/* Block or unblock output according to flow control. */
|
|
if (ISSET(msr, sc->sc_msr_cts)) {
|
|
sc->sc_tx_stopped = 0;
|
|
(*tp->t_linesw->l_start)(tp);
|
|
} else {
|
|
sc->sc_tx_stopped = 1;
|
|
}
|
|
}
|
|
|
|
#ifdef SCIF_DEBUG
|
|
if (scif_debug)
|
|
scifstatus(sc, "scif_stsoft");
|
|
#endif
|
|
#endif
|
|
}
|
|
|
|
#ifdef __HAVE_GENERIC_SOFT_INTERRUPTS
|
|
void
|
|
scifsoft(void *arg)
|
|
{
|
|
struct scif_softc *sc = arg;
|
|
struct tty *tp;
|
|
|
|
if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0)
|
|
return;
|
|
|
|
{
|
|
#else
|
|
void
|
|
#ifndef __NO_SOFT_SERIAL_INTERRUPT
|
|
scifsoft()
|
|
#else
|
|
scifsoft(void *arg)
|
|
#endif
|
|
{
|
|
struct scif_softc *sc;
|
|
struct tty *tp;
|
|
int unit;
|
|
#ifdef __NO_SOFT_SERIAL_INTERRUPT
|
|
int s;
|
|
|
|
s = splsoftserial();
|
|
scif_softintr_scheduled = 0;
|
|
#endif
|
|
|
|
for (unit = 0; unit < scif_cd.cd_ndevs; unit++) {
|
|
sc = scif_cd.cd_devs[unit];
|
|
if (sc == NULL || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK))
|
|
continue;
|
|
|
|
if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0)
|
|
continue;
|
|
|
|
tp = sc->sc_tty;
|
|
if (tp == NULL)
|
|
continue;
|
|
if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0)
|
|
continue;
|
|
#endif
|
|
tp = sc->sc_tty;
|
|
|
|
if (sc->sc_rx_ready) {
|
|
sc->sc_rx_ready = 0;
|
|
scif_rxsoft(sc, tp);
|
|
}
|
|
|
|
#if 0
|
|
if (sc->sc_st_check) {
|
|
sc->sc_st_check = 0;
|
|
scif_stsoft(sc, tp);
|
|
}
|
|
#endif
|
|
|
|
if (sc->sc_tx_done) {
|
|
sc->sc_tx_done = 0;
|
|
scif_txsoft(sc, tp);
|
|
}
|
|
}
|
|
|
|
#ifndef __HAVE_GENERIC_SOFT_INTERRUPTS
|
|
#ifdef __NO_SOFT_SERIAL_INTERRUPT
|
|
splx(s);
|
|
#endif
|
|
#endif
|
|
}
|
|
|
|
int
|
|
scifintr(void *arg)
|
|
{
|
|
struct scif_softc *sc = arg;
|
|
u_char *put, *end;
|
|
u_int cc;
|
|
u_short ssr2;
|
|
int count;
|
|
|
|
if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0)
|
|
return (0);
|
|
|
|
end = sc->sc_ebuf;
|
|
put = sc->sc_rbput;
|
|
cc = sc->sc_rbavail;
|
|
|
|
do {
|
|
ssr2 = SHREG_SCSSR2;
|
|
if (ISSET(ssr2, SCSSR2_BRK)) {
|
|
SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_DR);
|
|
#ifdef DDB
|
|
if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) {
|
|
console_debugger();
|
|
}
|
|
#endif /* DDB */
|
|
#ifdef KGDB
|
|
if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB)) {
|
|
kgdb_connect(1);
|
|
}
|
|
#endif /* KGDB */
|
|
}
|
|
count = SHREG_SCFDR2 & SCFDR2_RECVCNT;
|
|
if (count != 0) {
|
|
while (1) {
|
|
u_char c = SHREG_SCFRDR2;
|
|
u_char err = (u_char)(SHREG_SCSSR2 & 0x00ff);
|
|
|
|
SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_RDF | SCSSR2_DR);
|
|
#ifdef SH4
|
|
if (CPU_IS_SH4)
|
|
SHREG_SCLSR2 &= ~SCLSR2_ORER;
|
|
#endif
|
|
if ((cc > 0) && (count > 0)) {
|
|
put[0] = c;
|
|
put[1] = err;
|
|
put += 2;
|
|
if (put >= end)
|
|
put = sc->sc_rbuf;
|
|
cc--;
|
|
count--;
|
|
} else
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* Current string of incoming characters ended because
|
|
* no more data was available or we ran out of space.
|
|
* Schedule a receive event if any data was received.
|
|
* If we're out of space, turn off receive interrupts.
|
|
*/
|
|
sc->sc_rbput = put;
|
|
sc->sc_rbavail = cc;
|
|
if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED))
|
|
sc->sc_rx_ready = 1;
|
|
|
|
/*
|
|
* See if we are in danger of overflowing a buffer. If
|
|
* so, use hardware flow control to ease the pressure.
|
|
*/
|
|
if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) &&
|
|
cc < sc->sc_r_hiwat) {
|
|
SET(sc->sc_rx_flags, RX_IBUF_BLOCKED);
|
|
#if 0
|
|
scif_hwiflow(sc);
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* If we're out of space, disable receive interrupts
|
|
* until the queue has drained a bit.
|
|
*/
|
|
if (!cc) {
|
|
SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED);
|
|
SHREG_SCSCR2 &= ~SCSCR2_RIE;
|
|
}
|
|
} else {
|
|
if (SHREG_SCSSR2 & (SCSSR2_RDF | SCSSR2_DR)) {
|
|
SHREG_SCSCR2 &= ~(SCSCR2_TIE | SCSCR2_RIE);
|
|
delay(10);
|
|
SHREG_SCSCR2 |= SCSCR2_TIE | SCSCR2_RIE;
|
|
continue;
|
|
}
|
|
}
|
|
} while (SHREG_SCSSR2 & (SCSSR2_RDF | SCSSR2_DR));
|
|
|
|
#if 0
|
|
msr = bus_space_read_1(iot, ioh, scif_msr);
|
|
delta = msr ^ sc->sc_msr;
|
|
sc->sc_msr = msr;
|
|
if (ISSET(delta, sc->sc_msr_mask)) {
|
|
SET(sc->sc_msr_delta, delta);
|
|
|
|
/*
|
|
* Pulse-per-second clock signal on edge of DCD?
|
|
*/
|
|
if (ISSET(delta, sc->sc_ppsmask)) {
|
|
struct timeval tv;
|
|
if (ISSET(msr, sc->sc_ppsmask) ==
|
|
sc->sc_ppsassert) {
|
|
/* XXX nanotime() */
|
|
microtime(&tv);
|
|
TIMEVAL_TO_TIMESPEC(&tv,
|
|
&sc->ppsinfo.assert_timestamp);
|
|
if (sc->ppsparam.mode & PPS_OFFSETASSERT) {
|
|
timespecadd(&sc->ppsinfo.assert_timestamp,
|
|
&sc->ppsparam.assert_offset,
|
|
&sc->ppsinfo.assert_timestamp);
|
|
TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.assert_timestamp);
|
|
}
|
|
|
|
#ifdef PPS_SYNC
|
|
if (sc->ppsparam.mode & PPS_HARDPPSONASSERT)
|
|
hardpps(&tv, tv.tv_usec);
|
|
#endif
|
|
sc->ppsinfo.assert_sequence++;
|
|
sc->ppsinfo.current_mode =
|
|
sc->ppsparam.mode;
|
|
|
|
} else if (ISSET(msr, sc->sc_ppsmask) ==
|
|
sc->sc_ppsclear) {
|
|
/* XXX nanotime() */
|
|
microtime(&tv);
|
|
TIMEVAL_TO_TIMESPEC(&tv,
|
|
&sc->ppsinfo.clear_timestamp);
|
|
if (sc->ppsparam.mode & PPS_OFFSETCLEAR) {
|
|
timespecadd(&sc->ppsinfo.clear_timestamp,
|
|
&sc->ppsparam.clear_offset,
|
|
&sc->ppsinfo.clear_timestamp);
|
|
TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.clear_timestamp);
|
|
}
|
|
|
|
#ifdef PPS_SYNC
|
|
if (sc->ppsparam.mode & PPS_HARDPPSONCLEAR)
|
|
hardpps(&tv, tv.tv_usec);
|
|
#endif
|
|
sc->ppsinfo.clear_sequence++;
|
|
sc->ppsinfo.current_mode =
|
|
sc->ppsparam.mode;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Stop output immediately if we lose the output
|
|
* flow control signal or carrier detect.
|
|
*/
|
|
if (ISSET(~msr, sc->sc_msr_mask)) {
|
|
sc->sc_tbc = 0;
|
|
sc->sc_heldtbc = 0;
|
|
#ifdef SCIF_DEBUG
|
|
if (scif_debug)
|
|
scifstatus(sc, "scifintr ");
|
|
#endif
|
|
}
|
|
|
|
sc->sc_st_check = 1;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Done handling any receive interrupts. See if data can be
|
|
* transmitted as well. Schedule tx done event if no data left
|
|
* and tty was marked busy.
|
|
*/
|
|
if (((SHREG_SCFDR2 & SCFDR2_TXCNT) >> 8) != 16) { /* XXX (msaitoh) */
|
|
/*
|
|
* If we've delayed a parameter change, do it now, and restart
|
|
* output.
|
|
*/
|
|
if (sc->sc_heldchange) {
|
|
sc->sc_heldchange = 0;
|
|
sc->sc_tbc = sc->sc_heldtbc;
|
|
sc->sc_heldtbc = 0;
|
|
}
|
|
|
|
/* Output the next chunk of the contiguous buffer, if any. */
|
|
if (sc->sc_tbc > 0) {
|
|
int n;
|
|
int max;
|
|
int i;
|
|
|
|
n = sc->sc_tbc;
|
|
max = sc->sc_fifolen -
|
|
((SHREG_SCFDR2 & SCFDR2_TXCNT) >> 8);
|
|
if (n > max)
|
|
n = max;
|
|
|
|
for (i = 0; i < n; i++) {
|
|
scif_putc(*(sc->sc_tba));
|
|
sc->sc_tba++;
|
|
}
|
|
sc->sc_tbc -= n;
|
|
} else {
|
|
/* Disable transmit completion interrupts if necessary. */
|
|
#if 0
|
|
if (ISSET(sc->sc_ier, IER_ETXRDY))
|
|
#endif
|
|
SHREG_SCSCR2 &= ~SCSCR2_TIE;
|
|
|
|
if (sc->sc_tx_busy) {
|
|
sc->sc_tx_busy = 0;
|
|
sc->sc_tx_done = 1;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Wake up the poller. */
|
|
#ifdef __HAVE_GENERIC_SOFT_INTERRUPTS
|
|
softintr_schedule(sc->sc_si);
|
|
#else
|
|
#ifndef __NO_SOFT_SERIAL_INTERRUPT
|
|
setsoftserial();
|
|
#else
|
|
if (!scif_softintr_scheduled) {
|
|
scif_softintr_scheduled = 1;
|
|
callout_reset(&scif_soft_ch, 1, scifsoft, NULL);
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#if NRND > 0 && defined(RND_SCIF)
|
|
rnd_add_uint32(&sc->rnd_source, iir | lsr);
|
|
#endif
|
|
|
|
return (1);
|
|
}
|
|
|
|
void
|
|
scifcnprobe(struct consdev *cp)
|
|
{
|
|
int maj;
|
|
|
|
/* locate the major number */
|
|
maj = cdevsw_lookup_major(&scif_cdevsw);
|
|
|
|
/* Initialize required fields. */
|
|
cp->cn_dev = makedev(maj, 0);
|
|
#ifdef SCIFCONSOLE
|
|
cp->cn_pri = CN_REMOTE;
|
|
#else
|
|
cp->cn_pri = CN_NORMAL;
|
|
#endif
|
|
}
|
|
|
|
void
|
|
scifcninit(struct consdev *cp)
|
|
{
|
|
|
|
InitializeScif(scifcn_speed);
|
|
scifisconsole = 1;
|
|
}
|
|
|
|
int
|
|
scifcngetc(dev_t dev)
|
|
{
|
|
int c;
|
|
int s;
|
|
|
|
s = splserial();
|
|
c = scif_getc();
|
|
splx(s);
|
|
|
|
return (c);
|
|
}
|
|
|
|
void
|
|
scifcnputc(dev_t dev, int c)
|
|
{
|
|
int s;
|
|
|
|
s = splserial();
|
|
scif_putc((u_char)c);
|
|
splx(s);
|
|
}
|
|
|
|
#ifdef KGDB
|
|
int
|
|
scif_kgdb_init()
|
|
{
|
|
|
|
if (strcmp(kgdb_devname, "scif") != 0)
|
|
return (1);
|
|
|
|
if (scifisconsole)
|
|
return (1); /* can't share with console */
|
|
|
|
InitializeScif(kgdb_rate);
|
|
|
|
kgdb_attach((int (*)(void *))scifcngetc,
|
|
(void (*)(void *, int))scifcnputc, NULL);
|
|
kgdb_dev = 123; /* unneeded, only to satisfy some tests */
|
|
kgdb_attached = 1;
|
|
|
|
return (0);
|
|
}
|
|
#endif /* KGDB */
|