138 lines
5.0 KiB
C
138 lines
5.0 KiB
C
/*-
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)npx.h 5.3 (Berkeley) 1/18/91
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* $Id: npx.h,v 1.8 1994/01/17 18:10:01 jtc Exp $
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*/
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/*
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* 287/387 NPX Coprocessor Data Structures and Constants
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* W. Jolitz 1/90
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*/
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#ifndef _I386_NPX_H_
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#define _I386_NPX_H_
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/* Environment information of floating point unit */
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struct env87 {
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long en_cw; /* control word (16bits) */
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long en_sw; /* status word (16bits) */
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long en_tw; /* tag word (16bits) */
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long en_fip; /* floating point instruction pointer */
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u_short en_fcs; /* floating code segment selector */
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u_short en_opcode; /* opcode last executed (11 bits ) */
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long en_foo; /* floating operand offset */
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long en_fos; /* floating operand segment selector */
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};
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/* Contents of each floating point accumulator */
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struct fpacc87 {
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#ifdef dontdef /* too unportable */
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u_long fp_mantlo; /* mantissa low (31:0) */
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u_long fp_manthi; /* mantissa high (63:32) */
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int fp_exp:15; /* exponent */
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int fp_sgn:1; /* mantissa sign */
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#else
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u_char fp_bytes[10];
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#endif
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};
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/* Floating point context */
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struct save87 {
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struct env87 sv_env; /* floating point control/status */
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struct fpacc87 sv_ac[8]; /* accumulator contents, 0-7 */
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#ifndef dontdef
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u_long sv_ex_sw; /* status word for last exception (was pad) */
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u_long sv_ex_tw; /* tag word for last exception (was pad) */
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u_char sv_pad[8 * 2 - 2 * 4]; /* bogus historical padding */
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#endif
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};
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/* Cyrix EMC memory - mapped coprocessor context switch information */
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struct emcsts {
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long em_msw; /* memory mapped status register when swtched */
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long em_tar; /* memory mapped temp A register when swtched */
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long em_dl; /* memory mapped D low register when swtched */
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};
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/* Intel prefers long real (53 bit) precision */
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#define __iBCS_NPXCW__ 0x262
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/* wfj prefers temporary real (64 bit) precision */
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#define __386BSD_NPXCW__ 0x362
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/* */
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#define __NetBSD_NPXCW__ 0x137f
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/*
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* bde prefers 53 bit precision and all exceptions masked.
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*
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* The standard control word from finit is 0x37F, giving:
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*
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* round to nearest
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* 64-bit precision
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* all exceptions masked.
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*
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* Now I want:
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*
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* affine mode for 287's (if they work at all) (1 in bitfield 1<<12)
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* 53-bit precision (2 in bitfield 3<<8)
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* overflow exception unmasked (0 in bitfield 1<<3)
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* zero divide exception unmasked (0 in bitfield 1<<2)
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* invalid-operand exception unmasked (0 in bitfield 1<<0).
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*
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* 64-bit precision often gives bad results with high level languages
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* because it makes the results of calculations depend on whether
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* intermediate values are stored in memory or in FPU registers.
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*
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* The "Intel" and wfj control words have:
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*
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* underflow exception unmasked (0 in bitfield 1<<4)
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*
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* but that causes an unexpected exception in the test program 'paranoia'
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* and makes denormals useless (DBL_MIN / 2 underflows). It doesn't make
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* a lot of sense to trap underflow without trapping denormals.
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*
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* Later I will want the IEEE default of all exceptions masked. See the
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* 0.0 math manpage for why this is better. The 0.1 math manpage is empty.
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*/
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#define __BDE_NPXCW__ 0x1272
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#define __BETTER_BDE_NPXCW__ 0x127f
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#ifdef __NetBSD__
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#define __INITIAL_NPXCW__ __NetBSD_NPXCW__
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#else
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#define __INITIAL_NPXCW__ __iBCS_NPXCW__
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#endif
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#endif /* !_I386_NPX_H_ */
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