1045 lines
26 KiB
C
1045 lines
26 KiB
C
/* $NetBSD: dp.c,v 1.6 1994/10/26 08:24:10 cgd Exp $ */
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/* Written by Phil Nelson for the pc532. Used source with the following
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* copyrights as a model.
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*
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* dp.c: A NCR DP8490 driver for the pc532.
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*/
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/*
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* (Mostly) Written by Julian Elischer (julian@tfs.com)
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* for TRW Financial Systems for use under the MACH(2.5) operating system.
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*
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* TRW Financial Systems, in accordance with their agreement with Carnegie
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* Mellon University, makes this software available to CMU to distribute
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* or use in any manner that they see fit as long as this message is kept with
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* the software. For this reason TFS also grants any other persons or
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* organisations permission to use or modify this software.
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*
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* TFS supplies this software to be publicly redistributed
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* on the understanding that TFS is not responsible for the correct
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* functioning of this software in any circumstances.
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*
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*/
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/*
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* a FEW lines in this driver come from a MACH adaptec-disk driver
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* so the copyright below is included:
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*
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* Copyright 1990 by Open Software Foundation,
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* Grenoble, FRANCE
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*
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* All Rights Reserved
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*
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* Permission to use, copy, modify, and distribute this software and
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* its documentation for any purpose and without fee is hereby granted,
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* provided that the above copyright notice appears in all copies and
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* that both the copyright notice and this permission notice appear in
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* supporting documentation, and that the name of OSF or Open Software
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* Foundation not be used in advertising or publicity pertaining to
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* distribution of the software without specific, written prior
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* permission.
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*
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* OSF DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS,
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* IN NO EVENT SHALL OSF BE LIABLE FOR ANY SPECIAL, INDIRECT, OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
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* LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT,
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* NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION
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* WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/errno.h>
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#include <sys/ioctl.h>
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#include <sys/buf.h>
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#include <machine/stdarg.h>
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#include <sys/proc.h>
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#include <sys/user.h>
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#include <sys/dkbad.h>
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#include <sys/disklabel.h>
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#include <scsi/scsi_all.h>
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#include <scsi/scsiconf.h>
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#include <machine/frame.h>
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#include <machine/icu.h>
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#include "device.h"
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#include "dpreg.h"
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#define DP_DEBUG 0
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/* Some constants (may need to be changed!) */
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#define DP_NSEG 16
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int dpprobe(struct pc532_device *);
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int dpattach(struct pc532_device *);
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int dp_scsi_cmd(struct scsi_xfer *);
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void dpminphys(struct buf *);
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long int dp_adapter_info(int);
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void dp_intr(void);
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void dp_intr_work(void);
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struct scsidevs *
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scsi_probe(int masunit, struct scsi_switch *sw, int physid, int type, int want);
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struct pc532_driver dpdriver = {
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dpprobe, dpattach, "dp",
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};
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struct scsi_switch dp_switch = {
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"dp",
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dp_scsi_cmd,
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dpminphys,
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0,
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0,
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dp_adapter_info,
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0, 0, 0
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};
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/* Sense command. */
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static u_char sense_cmd[] = { 3, 0, 0, 0, 0, 0};
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/* Do we need to initialize. */
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int dp_needs_init = 1;
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/* Do we need a reset . */
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int dp_needs_reset = 1;
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/* SCSI phase we are currently in . . . */
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int dp_scsi_phase;
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/* SCSI Driver state */
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int dp_dvr_state = DP_DVR_READY;
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/* For polled error reporting. */
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int dp_intr_retval;
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/* For counting the retries. */
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int dp_try_count;
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/* Give the interrupt routine access to the current scsi_xfer info block. */
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struct scsi_xfer *cur_xs = NULL;
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/* names of phases for debug printouts */
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const char *dp_phase_names[] = {
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"DATA OUT",
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"DATA IN",
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"CMD",
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"STATUS",
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"PHASE 4",
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"PHASE 5",
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"MSG OUT",
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"MSG IN",
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};
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/* Initial probe for a device. If it is using the dp controller,
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just say yes so that attach can be the one to find the real drive. */
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int dpprobe(struct pc532_device *dvp)
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{
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/* If we call this, we need to add SPL_DP to the bio mask! */
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PL_bio |= SPL_DP;
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PL_zero |= PL_bio;
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if (dp_needs_init)
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dp_initialize();
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if (dp_needs_reset)
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dp_reset();
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/* All pc532s should have one, so we don't check ! :) */
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return (1);
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}
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int dpattach(struct pc532_device *dvp)
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{
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int r;
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r = scsi_attach(0, 7, &dp_switch,
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&dvp->pd_drive, &dvp->pd_unit, dvp->pd_flags);
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return(r);
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}
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void dpminphys(struct buf *bp)
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{
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if(bp->b_bcount > ((DP_NSEG - 1) * NBPG))
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bp->b_bcount = ((DP_NSEG - 1) * NBPG);
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}
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long int dp_adapter_info(int unit)
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{
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return (1); /* only 1 outstanding request. */
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}
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#if DP_DEBUG
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void
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dp_print_stat1(u_char stat1)
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{
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printf("stat1=");
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if ( stat1 & 0x80 ) printf(" /RST");
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if ( stat1 & 0x40 ) printf(" /BSY");
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if ( stat1 & 0x20 ) printf(" /REQ");
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if ( stat1 & 0x10 ) printf(" /MSG");
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if ( stat1 & 0x08 ) printf(" /CD");
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if ( stat1 & 0x04 ) printf(" /IO");
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if ( stat1 & 0x02 ) printf(" /SEL");
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if ( stat1 & 0x01 ) printf(" /DBP");
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printf("\n");
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}
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void
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dp_print_stat2(u_char stat2)
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{
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printf("stat2=");
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if ( stat2 & 0x80 ) printf(" EDMA");
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if ( stat2 & 0x40 ) printf(" DRQ");
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if ( stat2 & 0x20 ) printf(" SPER");
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if ( stat2 & 0x10 ) printf(" INT");
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if ( stat2 & 0x08 ) printf(" PHSM");
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if ( stat2 & 0x04 ) printf(" BSY");
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if ( stat2 & 0x02 ) printf(" /ATN");
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if ( stat2 & 0x01 ) printf(" /ACK");
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printf("\n");
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}
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#endif
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#if DP_DEBUG
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void
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dp_print_regs()
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{
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u_char stat1 = RD_ADR(u_char, DP_STAT1);
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u_char stat2 = RD_ADR(u_char, DP_STAT2);
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dp_print_stat1(stat1);
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dp_print_stat2(stat2);
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}
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#endif
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/* Do a scsi command. */
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int dp_scsi_cmd(struct scsi_xfer *xs)
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{
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struct iovec *iovp;
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int flags;
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int retval; /* Return values from functions. */
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int x; /* for splbio() & splhigh() */
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int dvr_state;
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int ti_val; /* For timeouts. */
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#if DP_DEBUG
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printf("\n");
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#endif
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x = splhigh();
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if (dp_dvr_state == DP_DVR_READY)
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dp_dvr_state = DP_DVR_STARTED;
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dvr_state = dp_dvr_state;
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splx(x);
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if (dvr_state != DP_DVR_STARTED)
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return (TRY_AGAIN_LATER);
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cur_xs = xs;
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/* Some initial checks. */
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flags = xs->flags;
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if (!(flags & INUSE)) {
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#if DP_DEBUG
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printf("dp xs not in use!\n");
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#endif
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xs->flags |= INUSE;
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}
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if (flags & ITSDONE) {
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#if DP_DEBUG
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printf("dp xs already done!\n");
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#endif
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xs->flags &= ~ITSDONE;
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}
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if (dp_needs_reset || (xs->flags & SCSI_RESET))
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dp_reset();
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#if DP_DEBUG
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printf ("scsi_cmd: flags=0x%x, targ=%d, lu=%d, cmdlen=%d, cmd=%x\n",
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xs->flags, xs->targ, xs->lu, xs->cmdlen, xs->cmd->opcode);
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#endif
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#if 1
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/* we don't always get NOMASK passed in, so this hack fakes it. */
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{
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if ( !initproc )
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xs->flags |= SCSI_NOMASK;
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}
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#endif
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if (!(xs->flags & SCSI_NOMASK)) {
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x = splbio();
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retval = dp_start_cmd(xs);
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splx(x);
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return retval;
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}
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/* No interrupts available! */
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retval = dp_start_cmd(xs);
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if (retval != SUCCESSFULLY_QUEUED)
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return retval;
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#if DP_DEBUG > 1
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printf("polling for interrupts\n");
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#endif
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ti_val = WAIT_MUL * xs->timeout;
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while (dp_dvr_state != DP_DVR_READY) {
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if (RD_ADR(u_char, DP_STAT2) & DP_S_IRQ) {
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dp_intr_work();
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ti_val = WAIT_MUL * xs->timeout;
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retval = dp_intr_retval;
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}
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if (--ti_val == 0) {
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/* Software Timeout! */
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xs->error = XS_SWTIMEOUT;
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dp_dvr_state = DP_DVR_READY;
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retval = HAD_ERROR;
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}
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}
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if (xs->error == XS_SWTIMEOUT) {
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/* Software Timeout! */
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printf ("scsi timeout!\n");
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#if DP_DEBUG
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dp_print_regs();
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printf("TCMD = 0x%x\n", RD_ADR(u_char, DP_TCMD));
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#endif
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dp_reset();
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}
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#if 1
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/* another hack: read cannot handle anything but SUCCESSFULLY_QUEUED */
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if (xs->cmd->opcode == 0x28)
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return SUCCESSFULLY_QUEUED;
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#endif
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return retval;
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}
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/*===========================================================================*
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* dp_intr *
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*===========================================================================*/
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/* This is where a lot of the work happens! This is called in non-interrupt
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mode when an interrupt would have happened. It is also the real interrupt
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routine. It uses dp_dvr_state to determine the next actions along with
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cur_xs->flags. */
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void dp_intr(void)
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{
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int x = splhigh();
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#if DP_DEBUG
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printf("\n REAL dp_intr\n");
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#endif
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dp_intr_work();
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splx(x);
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}
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void dp_intr_work(void)
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{
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u_char isr;
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u_char new_phase;
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u_char stat1;
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u_char stat2;
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static u_char status;
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static u_char message;
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int ret;
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scsi_select_ctlr (DP8490);
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WR_ADR(u_char, DP_EMR_ISR, DP_EF_ISR_NEXT);
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isr = RD_ADR (u_char, DP_EMR_ISR);
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dp_clear_isr();
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stat1 = RD_ADR(u_char, DP_STAT1);
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new_phase = (stat1 >> 2) & 7;
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#if DP_DEBUG
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printf ("dp_intr: dvr_state %d isr=0x%x new_phase = %d %s\n",
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dp_dvr_state, isr, new_phase, dp_phase_names[new_phase]);
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#if DP_DEBUG > 1
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dp_print_regs();
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#endif
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#endif
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#if 0
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/* de-assert the bus */
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WR_ADR(u_char, DP_ICMD, DP_EMODE);
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/* disable dma */
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RD_ADR(u_char, DP_MODE) &= ~DP_M_DMA;
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#endif
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if (isr & DP_ISR_BSYERR) {
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#if DP_DEBUG
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printf("dp_intr: Busy error\n");
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#endif
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}
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if (isr & DP_ISR_EDMA) {
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#if DP_DEBUG > 1
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printf("dp_intr: EDMA detected\n");
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#endif
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RD_ADR(u_char, DP_MODE) &= ~DP_M_DMA;
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WR_ADR(u_char, DP_ICMD, DP_EMODE);
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}
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if (!(isr & DP_ISR_APHS)) {
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#if DP_DEBUG > 1
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printf("dp_intr: Not an APHS!\n");
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printf("dp_intr: dvr_state %d isr=0x%x (exit)\n",
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dp_dvr_state, isr);
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#endif
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return;
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}
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switch (dp_dvr_state) {
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case DP_DVR_ARB: /* Next comes the command phase! */
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if (new_phase != DP_PHASE_CMD) {
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#if DP_DEBUG
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printf ("Phase mismatch cmd!\n");
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#endif
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goto phase_mismatch;
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}
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dp_dvr_state = DP_DVR_CMD;
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ret = dp_pdma_out(cur_xs->cmd, cur_xs->cmdlen, DP_PHASE_CMD);
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dp_clear_isr();
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break;
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case DP_DVR_CMD: /* Next comes the data i/o phase if needed. */
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/*
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* This state can potentially accept data in, data out,
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* or status for new_phase. data in or data out could
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* be skipped (new_phase is status) if an error was detected
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* in the command.
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*/
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if (cur_xs->flags & SCSI_DATA_UIO) {
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/* UIO work. */
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panic ("scsi uio");
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}
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if (new_phase == DP_PHASE_DATAI) {
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#if 1
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/* just a quick hack until we
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can trust flags to be correct
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*/
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if (!cur_xs->data) {
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#else
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if (!(cur_xs->flags & SCSI_DATA_IN)) {
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#endif
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#if DP_DEBUG
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printf("Phase mismatch in.\n");
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#endif
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goto phase_mismatch;
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}
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/* expect STAT phase next */
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dp_dvr_state = DP_DVR_DATA;
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ret = dp_pdma_in(cur_xs->data, cur_xs->datalen,
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DP_PHASE_DATAI);
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dp_clear_isr();
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break;
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}
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else if (new_phase == DP_PHASE_DATAO) {
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#if 1
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/* just a quick hack until we
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can trust flags to be correct
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*/
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if (!cur_xs->data) {
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#else
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if (!(cur_xs->flags & SCSI_DATA_OUT)) {
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#endif
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#if DP_DEBUG
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printf("Phase mismatch out.\n");
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#endif
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goto phase_mismatch;
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}
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/* expect STAT phase next */
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dp_dvr_state = DP_DVR_DATA;
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ret = dp_pdma_out(cur_xs->data, cur_xs->datalen,
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DP_PHASE_DATAO);
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dp_clear_isr();
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break;
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}
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/* Fall through to next phase. */
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case DP_DVR_DATA: /* Next comes the stat phase */
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if (new_phase != DP_PHASE_STATUS) {
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#if DP_DEBUG
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printf("Phase mismatch stat.\n");
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#endif
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goto phase_mismatch;
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}
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dp_dvr_state = DP_DVR_STAT;
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dp_pdma_in(&status, 1, DP_PHASE_STATUS);
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dp_clear_isr();
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#if DP_DEBUG > 1
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printf("status = 0x%x\n", status);
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#endif
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break;
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case DP_DVR_STAT:
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if (new_phase != DP_PHASE_MSGI) {
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#if DP_DEBUG
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printf ("msgi phase mismatch\n");
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#endif
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goto phase_mismatch;
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}
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dp_dvr_state = DP_DVR_MSGI;
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dp_pdma_in(&message, 1, DP_PHASE_MSGI);
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dp_clear_isr();
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#if DP_DEBUG > 1
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printf("message = 0x%x\n", message);
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#endif
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#if 0
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if (status != SCSI_OK && dp_try_count < cur_xs->retries) {
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printf("dp_intr: retry: dp_try_count = %d\n",
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dp_try_count);
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dp_restart_cmd();
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}
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#endif
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break;
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default:
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phase_mismatch:
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/* TEMP error generation!!! */
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dp_reset();
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dp_dvr_state = DP_DVR_READY;
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cur_xs->error = XS_DRIVER_STUFFUP;
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dp_intr_retval = HAD_ERROR;
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/* If this true interrupt code, call the done routine. */
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if (cur_xs->when_done) {
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(*(cur_xs->when_done))(cur_xs->done_arg, cur_xs->done_arg2);
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}
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}
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|
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if (dp_dvr_state == DP_DVR_MSGI) {
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#if DP_DEBUG > 1
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printf ("dvr_stat: dp_try_count = %d\n", dp_try_count);
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#endif
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WR_ADR (u_char, DP_MODE, 0); /* Turn off monbsy, dma, ... */
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if (status == SCSI_OK) {
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cur_xs->error = XS_NOERROR;
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dp_intr_retval = COMPLETE;
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} else if (status & SCSI_BUSY) {
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cur_xs->error = XS_BUSY;
|
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dp_intr_retval = HAD_ERROR;
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} else if (status & SCSI_CHECK) {
|
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/* Do a sense command. */
|
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cur_xs->error = XS_SENSE;
|
|
dp_intr_retval = HAD_ERROR;
|
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dp_get_sense (cur_xs);
|
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}
|
|
cur_xs->flags |= ITSDONE;
|
|
dp_dvr_state = DP_DVR_READY;
|
|
#if DP_DEBUG > 1
|
|
printf("calling wakeup on 0x%x\n", cur_xs);
|
|
#endif
|
|
wakeup((caddr_t) cur_xs);
|
|
/* If this true interrupt code, call the done routine. */
|
|
if (cur_xs->when_done) {
|
|
#if DP_DEBUG > 1
|
|
printf("dp_intr: calling when_done 0x%x\n", cur_xs->when_done);
|
|
#endif
|
|
(*(cur_xs->when_done))(cur_xs->done_arg, cur_xs->done_arg2);
|
|
}
|
|
}
|
|
#if DP_DEBUG > 1
|
|
printf ("exit dp_intr.\n");
|
|
#endif
|
|
}
|
|
|
|
|
|
/*===========================================================================*
|
|
* dp_initialize *
|
|
*===========================================================================*/
|
|
|
|
dp_initialize()
|
|
{
|
|
#if DP_DEBUG
|
|
printf("dp_initialize()\n");
|
|
#endif
|
|
scsi_select_ctlr (DP8490);
|
|
WR_ADR (u_char, DP_ICMD, DP_EMODE); /* Set Enhanced mode */
|
|
WR_ADR (u_char, DP_MODE, 0); /* Disable everything. */
|
|
WR_ADR (u_char, DP_EMR_ISR, DP_EF_RESETIP);
|
|
WR_ADR (u_char, DP_EMR_ISR, DP_EF_NOP);
|
|
WR_ADR (u_char, DP_SER, 0x80); /* scsi adr 7. */
|
|
dp_scsi_phase = DP_PHASE_NONE;
|
|
dp_needs_init = 0;
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* dp_reset *
|
|
*===========================================================================*/
|
|
|
|
/*
|
|
* Reset dp SCSI bus.
|
|
*/
|
|
|
|
dp_reset()
|
|
{
|
|
volatile int i;
|
|
int x = splbio();
|
|
|
|
scsi_select_ctlr (DP8490);
|
|
WR_ADR (u_char, DP_MODE, 0); /* get into harmless state */
|
|
WR_ADR (u_char, DP_OUTDATA, 0);
|
|
WR_ADR (u_char, DP_ICMD, DP_A_RST|DP_EMODE); /* assert RST on SCSI bus */
|
|
for (i = 55; i; --i); /* wait 25 usec */
|
|
WR_ADR (u_char, DP_ICMD, DP_EMODE); /* deassert RST, get off bus */
|
|
WR_ADR (u_char, DP_EMR_ISR, DP_EF_ISR_NEXT | DP_EMR_APHS);
|
|
WR_ADR (u_char, DP_EMR_ISR, DP_INT_MASK); /* set interrupt mask */
|
|
splx(x);
|
|
for (i = 800000; i; --i); /* wait 360 msec */
|
|
dp_needs_reset = 0;
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* dp_wait_bus_free *
|
|
*===========================================================================*/
|
|
/* Wait for the SCSI bus to become free. Currently polled because I am
|
|
* assuming a single initiator configuration -- so this code would not be
|
|
* running if the bus were busy.
|
|
*/
|
|
int
|
|
dp_wait_bus_free()
|
|
{
|
|
int i;
|
|
u_char stat1;
|
|
volatile int j;
|
|
|
|
/* get into a harmless state */
|
|
WR_ADR (u_char, DP_TCMD, 0);
|
|
WR_ADR (u_char, DP_MODE, 0); /* return to initiator mode */
|
|
WR_ADR (u_char, DP_ICMD, DP_EMODE); /* clear SEL, disable data out */
|
|
i = WAIT_MUL * 2000;
|
|
while (i--) {
|
|
/* Must be clear for 2 usec, so read twice */
|
|
stat1 = RD_ADR (u_char, DP_STAT1);
|
|
if (stat1 & (DP_S_BSY | DP_S_SEL)) continue;
|
|
for (j = 5; j; j--);
|
|
stat1 = RD_ADR (u_char, DP_STAT1);
|
|
if (stat1 & (DP_S_BSY | DP_S_SEL)) continue;
|
|
return OK;
|
|
}
|
|
#if DP_DEBUG
|
|
printf("wait bus free failed\n");
|
|
dp_print_stat1(stat1);
|
|
#endif
|
|
dp_needs_reset = 1;
|
|
return NOT_OK;
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* dp_select *
|
|
*===========================================================================*/
|
|
/* Select SCSI device, set up for command transfer.
|
|
*/
|
|
int
|
|
dp_select(adr)
|
|
long adr;
|
|
{
|
|
int i, stat1;
|
|
|
|
#if DP_DEBUG > 1
|
|
printf("dp_select(0x%x)\n", adr);
|
|
#endif
|
|
WR_ADR (u_char, DP_TCMD, 0); /* get to harmless state */
|
|
WR_ADR (u_char, DP_MODE, 0); /* get to harmless state */
|
|
WR_ADR (u_char, DP_OUTDATA, adr); /* SCSI bus address */
|
|
WR_ADR (u_char, DP_ICMD, DP_A_SEL | DP_ENABLE_DB | DP_EMODE);
|
|
for (i = 0;; ++i) { /* wait for target to assert SEL */
|
|
stat1 = RD_ADR (u_char, DP_STAT1);
|
|
if (stat1 & DP_S_BSY) break; /* select successful */
|
|
if (i > WAIT_MUL * 2000) { /* timeout */
|
|
u_char isr;
|
|
WR_ADR(u_char, DP_EMR_ISR, DP_EF_ISR_NEXT);
|
|
isr = RD_ADR (u_char, DP_EMR_ISR);
|
|
#if DP_DEBUG
|
|
printf ("SCSI: SELECT timeout adr %d\n", adr);
|
|
dp_print_regs();
|
|
printf("ICMD = 0x%x isr = 0x%x\n", RD_ADR(u_char, DP_ICMD), isr);
|
|
#endif
|
|
dp_reset();
|
|
return NOT_OK;
|
|
}
|
|
}
|
|
WR_ADR (u_char, DP_ICMD, DP_EMODE); /* clear SEL, disable data out */
|
|
WR_ADR (u_char, DP_OUTDATA, 0);
|
|
dp_clear_isr();
|
|
WR_ADR (u_char, DP_TCMD, 4); /* bogus phase, guarantee mismatch */
|
|
WR_ADR (u_char, DP_MODE, DP_M_BSY | DP_M_DMA);
|
|
return OK;
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* scsi_select_ctlr
|
|
*===========================================================================*/
|
|
/* Select a SCSI device.
|
|
*/
|
|
scsi_select_ctlr (ctlr)
|
|
int ctlr;
|
|
{
|
|
/* May need other stuff here to syncronize between dp & aic. */
|
|
|
|
RD_ADR (u_char, ICU_IO) &= ~ICU_SCSI_BIT; /* i/o, not port */
|
|
RD_ADR (u_char, ICU_DIR) &= ~ICU_SCSI_BIT; /* output */
|
|
if (ctlr == DP8490)
|
|
RD_ADR (u_char, ICU_DATA) &= ~ICU_SCSI_BIT; /* select = 0 for 8490 */
|
|
else
|
|
RD_ADR (u_char, ICU_DATA) |= ICU_SCSI_BIT; /* select = 1 for AIC6250 */
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* dp_start_cmd *
|
|
*===========================================================================*/
|
|
|
|
int dp_start_cmd(struct scsi_xfer *xs)
|
|
{
|
|
#if 0
|
|
WR_ADR (u_char, DP_OUTDATA, 1 << xs->targ); /* SCSI bus address */
|
|
WR_ADR (u_char, DP_EMR_ISR, DP_EF_ARB);
|
|
dp_dvr_state = DP_DVR_ARB;
|
|
#else
|
|
|
|
/* This is not the "right" way to start it. We should just have the
|
|
chip do the select for us and interrupt at the end. */
|
|
|
|
if (!dp_wait_bus_free()) {
|
|
#if DP_DEBUG
|
|
printf("dp_start_cmd: DP DRIVER BUSY\n");
|
|
#endif
|
|
xs->error = XS_BUSY;
|
|
return TRY_AGAIN_LATER;
|
|
}
|
|
|
|
if (!dp_select(1 << xs->targ)) {
|
|
#if DP_DEBUG
|
|
printf("dp_start_cmd: DP DRIVER STUFFUP\n");
|
|
#endif
|
|
xs->error = XS_DRIVER_STUFFUP;
|
|
return HAD_ERROR;
|
|
}
|
|
#endif
|
|
|
|
/* After selection, we now wait for the APHS interrupt! */
|
|
dp_dvr_state = DP_DVR_ARB; /* Just finished the select/arbitration */
|
|
dp_try_count = 1;
|
|
|
|
if (!(xs->flags & SCSI_NOMASK)) {
|
|
/* Set up the timeout! */
|
|
#if DP_DEBUG > 1
|
|
printf ("dp_start_cmd: dp timeouts not done\n");
|
|
#endif
|
|
}
|
|
return SUCCESSFULLY_QUEUED;
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* dp_restart_cmd *
|
|
*===========================================================================*/
|
|
|
|
int dp_restart_cmd()
|
|
{
|
|
#if 0
|
|
WR_ADR (u_char, DP_OUTDATA, xs->targ); /* SCSI bus address */
|
|
WR_ADR (u_char, DP_EMR_ISR, DP_EF_ARB);
|
|
dp_dvr_state = DP_DVR_ARB;
|
|
#endif
|
|
|
|
/* This is not the "right" way to start it. We should just have the
|
|
chip do the select for us and interrupt at the end. */
|
|
|
|
DELAY(50);
|
|
#if DP_DEBUG
|
|
printf ("restart .. stat1=0x%x stat2=0x%x\n", RD_ADR(u_char, DP_STAT1),
|
|
RD_ADR(u_char, DP_STAT2));
|
|
#endif
|
|
if (!dp_wait_bus_free()) {
|
|
cur_xs->error = XS_BUSY;
|
|
return;
|
|
}
|
|
|
|
#if DP_DEBUG
|
|
printf ("restart .1 stat1=0x%x stat2=0x%x\n", RD_ADR(u_char, DP_STAT1),
|
|
RD_ADR(u_char, DP_STAT2));
|
|
printf ("cur_xs->targ=%d\n",cur_xs->targ);
|
|
#endif
|
|
if (!dp_select (1 << cur_xs->targ)) {
|
|
cur_xs->error = XS_DRIVER_STUFFUP;
|
|
return;
|
|
}
|
|
|
|
#if DP_DEBUG
|
|
printf ("restart .2 stat1=0x%x stat2=0x%x\n", RD_ADR(u_char, DP_STAT1),
|
|
RD_ADR(u_char, DP_STAT2));
|
|
#endif
|
|
/* After selection, we now wait for the APHS interrupt! */
|
|
dp_dvr_state = DP_DVR_ARB; /* Just finished the select/arbitration */
|
|
dp_try_count++;
|
|
|
|
if (!(cur_xs->flags & SCSI_NOMASK)) {
|
|
/* Set up the timeout! */
|
|
#if DP_DEBUG
|
|
printf ("dp_restart_cmd: dp timeouts not done\n");
|
|
#endif
|
|
}
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* dp_pdma_out *
|
|
*===========================================================================*/
|
|
|
|
/* Note: in NetBSD, the scsi dma addresses are set by the mapping hardware
|
|
to inhibit cache. There is therefore, no need to worry about cache hits
|
|
during access to dma addresses. */
|
|
|
|
int dp_pdma_out(char *buf, int count, int phase)
|
|
{
|
|
int cnt;
|
|
int ret = OK;
|
|
u_int stat2;
|
|
|
|
#if DP_DEBUG
|
|
printf("dp_pdma_out: write %d bytes\n", count);
|
|
#endif
|
|
#if DP_DEBUG > 1
|
|
if (RD_ADR(u_char, DP_STAT2) & DP_S_IRQ)
|
|
printf("WARNING: stat2:IRQ set on call to dp_pdma_out\n");
|
|
#endif
|
|
|
|
/* Set it up. */
|
|
WR_ADR(u_char, DP_TCMD, phase);
|
|
RD_ADR(u_char, DP_MODE) |= DP_M_DMA;
|
|
WR_ADR(u_char, DP_ICMD, DP_ENABLE_DB | DP_EMODE);
|
|
WR_ADR(u_char, DP_START_SEND, 0);
|
|
|
|
/* Do the pdma: first longs, then bytes. */
|
|
while (count > sizeof(long)) {
|
|
WR_ADR(long, DP_DMA, *(((long *)buf)++));
|
|
count -= sizeof(long);
|
|
}
|
|
while (count-- > 1) {
|
|
WR_ADR(u_char, DP_DMA, *(buf++));
|
|
}
|
|
|
|
/* wait for DRQ to be asserted for the last byte, or an
|
|
* interrupt request to be signaled
|
|
*/
|
|
while (1) {
|
|
stat2 = RD_ADR(u_char, DP_STAT2);
|
|
if (stat2 & (DP_S_IRQ | DP_S_DRQ)) break;
|
|
}
|
|
|
|
if (stat2 & DP_S_DRQ) {
|
|
WR_ADR(u_char, DP_DMA_EOP, *buf);
|
|
}
|
|
else {
|
|
/* dma error! */
|
|
#if DP_DEBUG
|
|
printf ("dma write error!\n");
|
|
dp_print_stat1(RD_ADR(u_char, DP_STAT1));
|
|
dp_print_stat2(stat2);
|
|
#endif
|
|
cur_xs->error = XS_DRIVER_STUFFUP;
|
|
/* Clear dma mode, just in case, and disable the bus. */
|
|
RD_ADR (u_char, DP_MODE) &= ~DP_M_DMA;
|
|
WR_ADR (u_char, DP_ICMD, DP_EMODE);
|
|
ret = NOT_OK;
|
|
}
|
|
#if 0
|
|
/* Clear dma mode, just in case, and disable the bus. */
|
|
RD_ADR (u_char, DP_MODE) &= ~DP_M_DMA;
|
|
WR_ADR (u_char, DP_ICMD, DP_EMODE);
|
|
#endif
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* dp_pdma_in *
|
|
*===========================================================================*/
|
|
|
|
/* Note: in NetBSD, the scsi dma addresses are set by the mapping hardware
|
|
to inhibit cache. There is therefore, no need to worry about cache hits
|
|
during access to dma addresses. */
|
|
|
|
int dp_pdma_in(char *buf, int count, int phase)
|
|
{
|
|
int ret = OK;
|
|
int i_count = count;
|
|
u_int stat2;
|
|
u_char *dma_adr = (u_char *) DP_DMA; /* Address for last few bytes. */
|
|
|
|
#if DP_DEBUG > 1
|
|
printf("dp_pdma_in: read %d bytes\n", count);
|
|
#endif
|
|
/* Set it up. */
|
|
WR_ADR(u_char, DP_TCMD, phase);
|
|
RD_ADR(u_char, DP_MODE) |= DP_M_DMA;
|
|
WR_ADR(u_char, DP_EMR_ISR, DP_EF_START_RCV | DP_EMR_APHS);
|
|
|
|
/* Do the pdma */
|
|
while (count >= sizeof(long)) {
|
|
*(((long *)buf)++) = RD_ADR(long, DP_DMA);
|
|
count -= sizeof(long);
|
|
}
|
|
|
|
while (count-- > 0) {
|
|
*(buf++) = RD_ADR(u_char, (dma_adr++));
|
|
}
|
|
|
|
/* Clear dma mode, just in case, and disable the bus. */
|
|
RD_ADR(u_char, DP_MODE) &= ~DP_M_DMA;
|
|
WR_ADR(u_char, DP_ICMD, DP_EMODE);
|
|
return ret;
|
|
}
|
|
|
|
dp_wait_for_edma()
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < 1000000; ++i) {
|
|
u_char tcmd = RD_ADR(u_char, DP_TCMD);
|
|
if (tcmd & DP_TCMD_EDMA) {
|
|
#if DP_DEBUG > 1
|
|
printf("dp_wait_for_phase: EDMA detected\n");
|
|
#endif
|
|
RD_ADR(u_char, DP_MODE) &= ~DP_M_DMA;
|
|
WR_ADR(u_char, DP_ICMD, DP_EMODE);
|
|
return;
|
|
}
|
|
}
|
|
printf("wait for edma timeout\n");
|
|
#if DP_DEBUG
|
|
dp_print_regs();
|
|
#endif
|
|
panic("dp: wait for edma");
|
|
}
|
|
|
|
dp_wait_for_phase(u_char phase)
|
|
{
|
|
int i;
|
|
u_char isr;
|
|
|
|
#if DP_DEBUG > 1
|
|
printf("wait for phase %d...", phase);
|
|
#endif
|
|
/* set the TCR register */
|
|
WR_ADR(u_char, DP_TCMD, phase);
|
|
/* wait for phase match */
|
|
for (i = 0; i < 1000000; ++i) {
|
|
u_char stat2 = RD_ADR(u_char, DP_STAT2);
|
|
if (stat2 & DP_S_PHASE) {
|
|
#if DP_DEBUG > 1
|
|
printf("done\n");
|
|
#endif
|
|
/* completely clear the isr */
|
|
WR_ADR(u_char, DP_EMR_ISR, DP_EF_ISR_NEXT);
|
|
isr = RD_ADR (u_char, DP_EMR_ISR);
|
|
dp_clear_isr();
|
|
return;
|
|
}
|
|
}
|
|
printf("wait for phase %d timeout\n", phase);
|
|
#if DP_DEBUG
|
|
dp_print_regs();
|
|
#endif
|
|
panic("dp: wait for phase");
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* dp_get_sense *
|
|
*===========================================================================*/
|
|
|
|
dp_get_sense (struct scsi_xfer *xs)
|
|
{
|
|
u_char status;
|
|
u_char message;
|
|
u_char isr;
|
|
int ret;
|
|
|
|
bzero((u_char *) &xs->sense, sizeof(xs->sense));
|
|
|
|
/* completely clear the isr on entry */
|
|
WR_ADR(u_char, DP_EMR_ISR, DP_EF_ISR_NEXT);
|
|
isr = RD_ADR (u_char, DP_EMR_ISR);
|
|
dp_clear_isr();
|
|
|
|
RD_ADR(u_char, DP_MODE) &= ~DP_M_DMA;
|
|
WR_ADR(u_char, DP_ICMD, DP_EMODE);
|
|
|
|
#if DP_DEBUG > 2
|
|
printf ("sense 1: wait bus free\n");
|
|
#endif
|
|
if (!dp_wait_bus_free()) {
|
|
#if DP_DEBUG > 2
|
|
printf("sense 1: wait-bus-free failed\n");
|
|
#endif
|
|
xs->error = XS_BUSY;
|
|
return;
|
|
}
|
|
|
|
#if DP_DEBUG > 2
|
|
printf ("sense 2: select device\n");
|
|
#endif
|
|
if (!dp_select (1 << xs->targ)) {
|
|
#if DP_DEBUG
|
|
printf("sense 2: select failed\n");
|
|
#endif
|
|
xs->error = XS_DRIVER_STUFFUP;
|
|
return;
|
|
}
|
|
/* completely clear the isr */
|
|
WR_ADR(u_char, DP_EMR_ISR, DP_EF_ISR_NEXT);
|
|
isr = RD_ADR (u_char, DP_EMR_ISR);
|
|
dp_clear_isr();
|
|
|
|
/* send the command */
|
|
sense_cmd[1] = xs->lu << 5;
|
|
#if 0
|
|
sense_cmd[4] = sizeof(struct scsi_sense_data);
|
|
#else
|
|
sense_cmd[4] = 0x04;
|
|
#endif
|
|
dp_wait_for_phase(DP_PHASE_CMD);
|
|
ret = dp_pdma_out(sense_cmd, sizeof(sense_cmd), DP_PHASE_CMD);
|
|
if (ret != OK) {
|
|
#if DP_DEBUG
|
|
printf("dp_pdma_out: ret=%d\n", ret);
|
|
#endif
|
|
return;
|
|
}
|
|
|
|
/* read sense data */
|
|
dp_wait_for_edma();
|
|
dp_wait_for_phase(DP_PHASE_DATAI);
|
|
ret = dp_pdma_in((u_char *) &xs->sense, sense_cmd[4], DP_PHASE_DATAI);
|
|
if (ret != OK) {
|
|
#if DP_DEBUG
|
|
printf ("dp_pdma_in: ret=%d\n", ret);
|
|
#endif
|
|
}
|
|
|
|
/* read status */
|
|
dp_wait_for_phase(DP_PHASE_STATUS);
|
|
ret = dp_pdma_in(&status, 1, DP_PHASE_STATUS);
|
|
if (ret != OK) {
|
|
#if DP_DEBUG
|
|
printf ("dp_pdma_in: ret=%d\n", ret);
|
|
#endif
|
|
}
|
|
|
|
/* read message */
|
|
dp_wait_for_phase(DP_PHASE_MSGI);
|
|
ret = dp_pdma_in(&message, 1, DP_PHASE_MSGI);
|
|
if (ret != OK) {
|
|
#if DP_DEBUG
|
|
printf ("dp_pdma_in: ret=%d\n", ret);
|
|
#endif
|
|
}
|
|
|
|
#if DP_DEBUG
|
|
printf("sense status = 0x%x\n", status);
|
|
printf(" sense (0x%x) valid = %d code = 0x%x class = 0x%x\n",
|
|
*(u_char *) &xs->sense,
|
|
xs->sense.valid, xs->sense.error_code, xs->sense.error_class);
|
|
#endif
|
|
|
|
if (status & SCSI_BUSY) {
|
|
xs->error = XS_BUSY;
|
|
}
|
|
WR_ADR (u_char, DP_MODE, 0); /* Turn off monbsy, dma, ... */
|
|
}
|