207 lines
8.1 KiB
C
207 lines
8.1 KiB
C
/*
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Tim L. Tucker.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* A lot of this was derived from if_wereg.h and 3c503.asm.
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*/
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/*
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* receive ring discriptor
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*
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* The National Semiconductor DS8390 Network interface controller uses
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* the following receive ring headers. The way this works is that the
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* memory on the interface card is chopped up into 256 bytes blocks.
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* A contiguous portion of those blocks are marked for receive packets
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* by setting start and end block #'s in the NIC. For each packet that
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* is put into the receive ring, one of these headers (4 bytes each) is
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* tacked onto the front.
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*/
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struct ec_ring {
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struct ecr_status { /* received packet status */
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u_char rs_prx:1, /* packet received intack */
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rs_crc:1, /* crc error */
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rs_fae:1, /* frame alignment error */
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rs_fo:1, /* fifo overrun */
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rs_mpa:1, /* packet received intack */
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rs_phy:1, /* packet received intack */
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rs_dis:1, /* packet received intack */
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rs_dfr:1; /* packet received intack */
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} ec_rcv_status; /* received packet status */
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u_char ec_next_packet; /* pointer to next packet */
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u_short ec_count; /* bytes in packet (length + 4) */
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};
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#define EC_PAGE_SIZE 256
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#define EC_TXBUF_SIZE 0x06
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#define EC_VMEM_OFFSET 0x20
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#define EC_RXBUF_OFFSET 0x26
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#define EC_RXBUF_END 0x40
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#define EC_ROM_OFFSET 8
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#define ETHER_ADDR_LEN 6
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#define ETHER_MIN_LEN 64
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#define ETHER_HDR_SIZE 14
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/*
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* Share memory management parameters.
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*/
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#define XMIT_MTU 0x600
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#define SM_TSTART_PG 0x020
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#define SM_RSTART_PG 0x026
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#define SM_RSTOP_PG 0x040
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/*
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* Description of header of each packet in receive area of shared memory.
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*/
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#define EN_RBUF_STAT 0x0 /* Received frame status. */
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#define EN_RBUF_NXT_PG 0x1 /* Page after this frame */
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#define EN_RBUF_SIZE_LO 0x2 /* Length of this frame */
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#define EN_RBUF_SIZE_HI 0x3 /* Length of this frame */
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#define EN_RBUF_NHDR 0x4 /* Length of above header area */
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/*
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* E33 Control registers. (base + 40x)
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*/
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#define E33G 0x0
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#define E33G_STARTPG 0x0
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#define E33G_STOPPG 0x1
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#define E33G_NBURST 0x2
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#define E33G_IOBASE 0x3
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#define E33G_ROMBASE 0x4
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#define E33G_GACFR 0x5
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#define E33G_CNTRL 0x6
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#define E33G_STATUS 0x7
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#define E33G_IDCFR 0x8
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#define E33G_DMAAH 0x9
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#define E33G_DMAAL 0xa
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#define E33G_VP2 0xb
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#define E33G_VP1 0xc
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#define E33G_VP0 0xd
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#define E33G_FIFOH 0xe
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#define E33G_FIFOL 0xf
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/*
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* Bits in E33G_GACFR register.
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*/
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#define EGACFR_NORM 0x49
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#define EGACFR_IRQOFF 0xc9
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/*
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* Control bits for E33G_CNTRL
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*/
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#define ECNTRL_RESET 0x01 /* Software reset of ASIC and 8390. */
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#define ECNTRL_THIN 0x02 /* Enable thinnet interface. */
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#define ECNTRL_SAPROM 0x04 /* Map Address Prom. */
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#define ECNTRL_DBLBFR 0x20 /* FIFO Configuration bit */
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#define ECNTRL_OUTPUT 0x40 /* PC->3c503 direction if set*/
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#define ECNTRL_START 0x80 /* Start DMA Logic. */
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/*
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* Bits in E33G status register.
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*/
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#define ESTAT_DPRDY 0x80 /* Data port of FIFO ready */
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#define ESTAT_UFLW 0x40 /* Tried to read FIFO when it was empty. */
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#define ESTAT_OFLW 0x20 /* Tried to write FIFO when it was full */
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#define ESTAT_DTC 0x10 /* Terminal count from PC bus DMA Logic */
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#define ESTAT_DIP 0x8 /* DMA in progress */
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/*
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* 8390 chip registers.
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*/
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#define EN_CCMD 0x0 /* Chip's command register. */
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#define EN0_STARTPG 0x1 /* Starting page of ring buffer. */
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#define EN0_STOPPG 0x2 /* Ending page + 1 of ring buffer */
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#define EN0_BOUNDARY 0x3 /* Boundary page of ring buffer */
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#define EN0_TSR 0x4 /* Transmit status register. */
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#define EN0_TPSR 0x4 /* Transmit starting page. */
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#define EN0_TCNTLO 0x5 /* Low byte of tx byte count */
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#define EN0_TCNTHI 0x6 /* High byte of tx byte count */
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#define EN0_ISR 0x7 /* Interrupt status register. */
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#define EN0_RSARLO 0x8 /* Remote start address reg 0 */
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#define EN0_RSARHI 0x9 /* Remote start address reg 1 */
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#define EN0_RCNTLO 0xa /* Remote byte count reg */
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#define EN0_RCNTHI 0xb /* Remote byte count reg */
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#define EN0_RXCR 0xc /* RX Control reg */
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#define EN0_TXCR 0xd /* TX Control reg */
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#define EN0_COUNTER0 0xd /* Rcv alignment error counter */
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#define EN0_DCFG 0xe /* Data configuration reg */
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#define EN0_COUNTER1 0xe /* rcv CRC error counter */
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#define EN0_IMR 0xf /* Interrupt mask reg */
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#define EN0_COUNTER2 0xf /* rcv missed frame error counter */
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#define EN1_PHYS 0x1 /* boards physical enet addr. */
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#define EN1_CURPAG 0x7 /* current memory page. */
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#define EN1_MULT 0x8 /* multicast filter mask array (8 bytes) */
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/*
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* Chip commands in EN_CCMD
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*/
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#define ENC_STOP 0x1 /* Stop the chip. */
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#define ENC_START 0x2 /* Start the chip */
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#define ENC_TRANS 0x4 /* Transmit a frame. */
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#define ENC_RREAD 0x8 /* Remote read. */
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#define ENC_RWRITE 0x10 /* Remote write */
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#define ENC_NODMA 0x20 /* No remote DMA used on this card */
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#define ENC_PAGE0 0x0 /* Select page 0 of chip regs */
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#define ENC_PAGE1 0x40 /* Select page 1 of chip regs */
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/*
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* Commands for RX control reg
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*/
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#define ENRXCR_MON 0x20 /* Monitor mode (no packets rcvd) */
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#define ENRXCR_PROMP 0x10 /* Promiscuous phys addresses. */
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#define ENRXCR_MULTI 0x8 /* Multicast (if pass filter) */
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#define ENRXCR_BCST 0x4 /* Accept broadcasts */
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#define ENRXCR_BAD 0x3 /* Accept runts and bad CRC frames */
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/*
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* Commands for TX control reg
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*/
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#define ENTXCR_LOOP 0x2 /* Set loopback mode */
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/*
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* bits on the EN0_DCFG config register.
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*/
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#define ENDCFG_BM8 0x48 /* Set bust mode, 8 deep FIFO */
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/*
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* Bits in the EN0_ISR Interrup Status Register
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*/
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#define ENISR_RX 0x1 /* receiver, no error */
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#define ENISR_TX 0x2 /* transmitter, no error */
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#define ENISR_RX_ERR 0x4 /* Receiver with error */
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#define ENISR_TX_ERR 0x8 /* Transmitter with error */
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#define ENISR_OVER 0x10 /* receiver overwrote the ring */
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#define ENISR_COUNTERS 0x20 /* Counters need emptying. */
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#define ENISR_RDC 0x40 /* Remote DMA complete. */
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#define ENISR_RESET 0x80 /* Reset completed */
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#define ENISR_ALL 0x3f /* Interrupts we will enable */
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/*
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* Bits in received packet status byte and EN0_RSR
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*/
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#define ENPS_RXOK 0x1 /* received a good packet */
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/*
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* Bits in TX status reg.
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*/
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#define ENTSR_PTX 0x1 /* Packet transmitted without error */
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#define ENTSR_COLL 0x4 /* Collided at least once */
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#define ENTSR_COLL16 0x8 /* Collided 16 times and was dropped */
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#define ENTSR_FU 0x20 /* TX FIFO Underrun */
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