197 lines
6.0 KiB
C
197 lines
6.0 KiB
C
/*-
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)icu.h 5.6 (Berkeley) 5/9/91
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*/
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/*
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* AT/386 Interrupt Control constants
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* W. Jolitz 8/89
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*/
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#ifndef __ICU__
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#define __ICU__
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#ifndef LOCORE
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/*
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* Interrupt "level" mechanism variables, masks, and macros
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*/
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extern unsigned short imen; /* interrupt mask enable */
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extern unsigned short cpl; /* current priority level mask */
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extern unsigned short highmask; /* group of interrupts masked with splhigh() */
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extern unsigned short ttymask; /* group of interrupts masked with spltty() */
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extern unsigned short biomask; /* group of interrupts masked with splbio() */
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extern unsigned short netmask; /* group of interrupts masked with splimp() */
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#define INTREN(s) imen &= ~(s)
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#define INTRDIS(s) imen |= (s)
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#define INTRMASK(msk,s) msk |= (s)
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#else
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/*
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* Macro's for interrupt level priority masks (used in interrupt vector entry)
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*/
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/* Mask a group of interrupts atomically */
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#define INTR(unit,mask,offst) \
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pushl $0 ; \
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pushl $ T_ASTFLT ; \
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pushal ; \
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nop ; \
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inb $0x84, %al ; /* ... ASAP */ \
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movb $0x20, %al ; /* next, as soon as possible send EOI ... */ \
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outb %al, $ IO_ICU1 ; /* ... so in service bit may be cleared ...*/ \
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inb $0x84, %al ; /* ... ASAP */ \
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movb $0x20, %al ; /* likewise, the other one as well */ \
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outb %al,$ IO_ICU2 ; \
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inb $0x84,%al ; \
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pushl %ds ; /* save our data and extra segments ... */ \
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pushl %es ; \
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movw $0x10, %ax ; /* ... and reload with kernel's own */ \
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movw %ax, %ds ; \
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movw %ax, %es ; \
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incl _cnt+V_INTR ; /* tally interrupts */ \
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incl _isa_intr + offst * 4 ; \
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inb $0x84,%al ; \
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movzwl _cpl,%eax ; \
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pushl %eax ; \
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pushl $ unit ; \
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orw mask ,%ax ; \
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movw %ax,_cpl ; \
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orw _imen,%ax ; \
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outb %al,$ IO_ICU1+1 ; \
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inb $0x84,%al ; \
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movb %ah,%al ; \
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outb %al,$ IO_ICU2+1 ; \
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inb $0x84,%al ; \
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sti
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/* Mask a group of interrupts atomically */
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#define INTRSTRAY(unit,mask,offst) \
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pushl $0 ; \
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pushl $ T_ASTFLT ; \
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pushal ; \
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nop ; \
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inb $0x84, %al ; /* ... ASAP */ \
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movb $3, %al ; /* look at ISR ... */ \
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outb %al, $ IO_ICU1 ; /* ... ...*/ \
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inb $0x84, %al ; /* ... ASAP */ \
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movb $3, %al ; /* look at ISR ... */ \
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outb %al, $ IO_ICU2 ; /* ... ...*/ \
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inb $0x84, %al ; /* ... ASAP */ \
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inb $ IO_ICU1, %al ; /* grab ISR */ \
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movb %al, %dl ; /* grab ISR */ \
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inb $0x84, %al ; /* ... ASAP */ \
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movb $2, %al ; /* back to look at IRR ... */ \
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outb %al, $ IO_ICU1 ; /* ... ...*/ \
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inb $0x84, %al ; /* ... ASAP */ \
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movb $2, %al ; /* back to look at IRR ... */ \
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outb %al, $ IO_ICU2 ; /* ... ...*/ \
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inb $0x84, %al ; /* ... ASAP */ \
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inb $ IO_ICU2, %al ; /* grab ISR */ \
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movb %al, %dh ; /* grab ISR */ \
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inb $0x84, %al ; /* ... ASAP */ \
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movb $0x20, %al ; /* next, as soon as possible send EOI ... */ \
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outb %al, $ IO_ICU1 ; /* ... so in service bit may be cleared ...*/ \
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inb $0x84, %al ; /* ... ASAP */ \
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movb $0x20, %al ; /* likewise, the other one as well */ \
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outb %al,$ IO_ICU2 ; \
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inb $0x84,%al ; \
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pushl %ds ; /* save our data and extra segments ... */ \
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pushl %es ; \
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movw $0x10, %ax ; /* ... and reload with kernel's own */ \
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movw %ax, %ds ; \
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movw %ax, %es ; \
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inb $0x84,%al ; \
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movzwl _cpl,%eax ; \
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pushl %eax ; \
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movzwl %dx,%eax ; \
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shll $8,%eax ; \
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movb $ unit , %al ; \
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pushl %eax ; \
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orw mask ,%ax ; \
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movw %ax,_cpl ; \
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orw _imen,%ax ; \
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outb %al,$ IO_ICU1+1 ; \
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inb $0x84,%al ; \
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movb %ah,%al ; \
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outb %al,$ IO_ICU2+1 ; \
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inb $0x84,%al ; \
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sti
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/* Interrupt vector exit macros */
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/* First eight interrupts (ICU1) */
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#define INTREXIT1 \
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jmp doreti
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/* Second eight interrupts (ICU2) */
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#define INTREXIT2 \
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jmp doreti
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#endif
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/*
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* Interrupt enable bits -- in order of priority
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*/
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#define IRQ0 0x0001 /* highest priority - timer */
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#define IRQ1 0x0002
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#define IRQ_SLAVE 0x0004
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#define IRQ8 0x0100
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#define IRQ9 0x0200
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#define IRQ2 IRQ9
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#define IRQ10 0x0400
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#define IRQ11 0x0800
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#define IRQ12 0x1000
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#define IRQ13 0x2000
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#define IRQ14 0x4000
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#define IRQ15 0x8000
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#define IRQ3 0x0008
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#define IRQ4 0x0010
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#define IRQ5 0x0020
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#define IRQ6 0x0040
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#define IRQ7 0x0080 /* lowest - parallel printer */
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/*
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* Interrupt Control offset into Interrupt descriptor table (IDT)
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*/
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#define ICU_OFFSET 32 /* 0-31 are processor exceptions */
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#define ICU_LEN 16 /* 32-47 are ISA interrupts */
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#endif __ICU__
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