109 lines
4.8 KiB
C
109 lines
4.8 KiB
C
/*
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* Copyright (C) 1993 Allen K. Briggs, Chris P. Caputo,
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* Michael L. Finch, Bradley A. Grantham, and
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* Lawrence A. Kesteloot
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the Alice Group.
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* 4. The names of the Alice Group or any of its members may not be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE ALICE GROUP ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE ALICE GROUP BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: serreg.h,v 1.4 1994/07/10 16:56:00 briggs Exp $
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*
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* Mac II serial device interface
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*
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* Information used in this source was gleaned from low-memory
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* global variables in MacOS and the Advanced Micro Devices
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* 1992 Data Book/Handbook.
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*/
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/* Gleaned from MacOS */
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extern volatile unsigned char *sccA;
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#define SER_W0_RSTESINTS 0x10 /* Reset ext/status interrupts */
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#define SER_W0_ENBRXRDY 0x20 /* Enable interrupt on next receive */
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#define SER_W0_RSTTXPND 0x28 /* Reset transmit interrupt pending */
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#define SER_W0_RSTERR 0x30 /* Reset error */
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#define SER_W0_RSTIUS 0x38 /* Reset highest interrupt pending */
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#define SER_W0_RSTTXUNDERRUN 0xc0 /* Reset transmit underrun/EOM latch */
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#define SER_W1_ENBEXTINT 0x01 /* Enable external int */
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#define SER_W1_ENBTXINT 0x02 /* Enable transmit ready interrupt */
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#define SER_W1_ENBR1INT 0x08 /* Rx Int on first char/special cond */
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#define SER_W1_ENBRXINT 0x10 /* Rx Int on all chars/special cond */
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#define SER_W3_ENBRX 0x01 /* Enable reception */
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#define SER_W3_RX5DBITS 0x00 /* Receive 5 data bits */
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#define SER_W3_RX6DBITS 0x80 /* Receive 6 data bits */
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#define SER_W3_RX7DBITS 0x40 /* Receive 7 data bits */
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#define SER_W3_RX8DBITS 0xC0 /* Receive 8 data bits */
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#define SER_W4_PARNONE 0x00 /* No parity */
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#define SER_W4_PARODD 0x01 /* Odd parity */
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#define SER_W4_PAREVEN 0x03 /* Even parity */
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#define SER_W4_1SBIT 0x04 /* 1 stop bit */
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#define SER_W4_2SBIT 0x0c /* 2 stop bits */
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#define SER_W5_RTS 0x02 /* RTS enable */
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#define SER_W5_ENBTX 0x08 /* Enable transmission */
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#define SER_W5_BREAK 0x10 /* Send break */
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#define SER_W5_TX5DBITS 0x00 /* Send 5 data bits */
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#define SER_W5_TX6DBITS 0x40 /* Send 6 data bits */
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#define SER_W5_TX7DBITS 0x20 /* Send 7 data bits */
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#define SER_W5_TX8DBITS 0x60 /* Send 8 data bits */
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#define SER_W5_DTR 0x80 /* DTR enable */
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#define SER_W9_HWRESET 0xC0 /* Force Hardware Reset */
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#define SER_W9_NV 0x02 /* There is no interrupt vector */
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#define SER_W9_DLC 0x04 /* Disable lower interrupt chain */
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#define SER_W9_MIE 0x08 /* Enable master interrupt */
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#define SER_W10_NRZ 0x00 /* Set NRZ encoding */
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#define SER_W11_TXBR 0x80 /* Transmit clock is BR generator */
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#define SER_W11_RXBR 0x40 /* Receive clock is BR generator */
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#define SER_W14_ENBBR 0x01 /* Enable BR generator */
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#define SER_W15_ABRTINT 0x80 /* Abort pending interrups */
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#define SER_R0_RXREADY 0x01 /* Received character available */
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#define SER_R0_TXREADY 0x04 /* Ready to transmit character */
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#define SER_R0_DCD 0x08 /* Carrier detect */
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#define SER_R0_CTS 0x20 /* Clear to send */
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#define SER_R0_TXUNDERRUN 0x40 /* Tx Underrun/EOM */
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#define SER_R1_RXOVERRUN 0x20
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#define SER_R1_PARITYERR 0x10
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#define SER_R1_CRCERR 0x40
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#define SER_R1_ENDOFFRAME 0x80
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#define SERBRD(x) (mac68k_machine.sccClkConst / (x) - 2)
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#define SCCCNTL(unit) (sccA[2 - ((unit) << 1)])
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#define SCCRDWR(unit) (sccA[6 - ((unit) << 1)])
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#define SER_DOCNTL(unit, reg, val) \
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{SCCCNTL(unit) = (reg); SCCCNTL(unit) = (val);}
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#define SER_STATUS(unit, reg) \
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(SCCCNTL(unit) = (reg), SCCCNTL(unit))
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