287 lines
7.7 KiB
C
287 lines
7.7 KiB
C
/* $NetBSD: ispmbox.h,v 1.2 1997/03/12 21:06:57 cgd Exp $ */
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/*
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* Mailbox and Command Definitions for for Qlogic ISP SCSI adapters.
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*
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* Copyright (c) 1997 by Matthew Jacob
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* NASA/Ames Research Center
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice immediately at the beginning of the file, without modification,
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* this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _ISPMBOX_H
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#define _ISPMBOX_H
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/*
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* Mailbox Command Opcodes
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*/
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#define MBOX_NO_OP 0x0000
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#define MBOX_LOAD_RAM 0x0001
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#define MBOX_EXEC_FIRMWARE 0x0002
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#define MBOX_DUMP_RAM 0x0003
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#define MBOX_WRITE_RAM_WORD 0x0004
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#define MBOX_READ_RAM_WORD 0x0005
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#define MBOX_MAILBOX_REG_TEST 0x0006
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#define MBOX_VERIFY_CHECKSUM 0x0007
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#define MBOX_ABOUT_FIRMWARE 0x0008
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/* 9 */
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/* a */
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/* b */
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/* c */
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/* d */
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#define MBOX_CHECK_FIRMWARE 0x000e
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/* f */
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#define MBOX_INIT_REQ_QUEUE 0x0010
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#define MBOX_INIT_RES_QUEUE 0x0011
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#define MBOX_EXECUTE_IOCB 0x0012
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#define MBOX_WAKE_UP 0x0013
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#define MBOX_STOP_FIRMWARE 0x0014
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#define MBOX_ABORT 0x0015
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#define MBOX_ABORT_DEVICE 0x0016
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#define MBOX_ABORT_TARGET 0x0017
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#define MBOX_BUS_RESET 0x0018
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#define MBOX_STOP_QUEUE 0x0019
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#define MBOX_START_QUEUE 0x001a
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#define MBOX_SINGLE_STEP_QUEUE 0x001b
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#define MBOX_ABORT_QUEUE 0x001c
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#define MBOX_GET_DEV_QUEUE_STATUS 0x001d
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/* 1e */
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#define MBOX_GET_FIRMWARE_STATUS 0x001f
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#define MBOX_GET_INIT_SCSI_ID 0x0020
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#define MBOX_GET_SELECT_TIMEOUT 0x0021
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#define MBOX_GET_RETRY_COUNT 0x0022
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#define MBOX_GET_TAG_AGE_LIMIT 0x0023
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#define MBOX_GET_CLOCK_RATE 0x0024
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#define MBOX_GET_ACT_NEG_STATE 0x0025
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#define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026
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#define MBOX_GET_SBUS_PARAMS 0x0027
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#define MBOX_GET_TARGET_PARAMS 0x0028
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#define MBOX_GET_DEV_QUEUE_PARAMS 0x0029
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/* 2a */
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/* 2b */
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/* 2c */
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/* 2d */
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/* 2e */
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/* 2f */
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#define MBOX_SET_INIT_SCSI_ID 0x0030
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#define MBOX_SET_SELECT_TIMEOUT 0x0031
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#define MBOX_SET_RETRY_COUNT 0x0032
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#define MBOX_SET_TAG_AGE_LIMIT 0x0033
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#define MBOX_SET_CLOCK_RATE 0x0034
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#define MBOX_SET_ACTIVE_NEG_STATE 0x0035
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#define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036
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#define MBOX_SET_SBUS_CONTROL_PARAMS 0x0037
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#define MBOX_SET_TARGET_PARAMS 0x0038
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#define MBOX_SET_DEV_QUEUE_PARAMS 0x0039
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/* 3a */
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/* 3b */
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/* 3c */
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/* 3d */
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/* 3e */
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/* 3f */
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#define MBOX_RETURN_BIOS_BLOCK_ADDR 0x0040
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#define MBOX_WRITE_FOUR_RAM_WORDS 0x0041
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#define MBOX_EXEC_BIOS_IOCB 0x0042
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#define MBOX_BUSY 0x04
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typedef struct {
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u_int16_t param[6];
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} mbreg_t;
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/*
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* Command Structure Definitions
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*/
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typedef struct {
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u_int32_t ds_base;
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u_int32_t ds_count;
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} ispds_t;
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typedef struct {
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#if BYTE_ORDER == BIG_ENDIAN
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u_int8_t rqs_entry_count;
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u_int8_t rqs_entry_type;
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u_int8_t rqs_flags;
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u_int8_t rqs_seqno;
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#else
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u_int8_t rqs_entry_type;
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u_int8_t rqs_entry_count;
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u_int8_t rqs_seqno;
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u_int8_t rqs_flags;
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#endif
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} isphdr_t;
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/* RQS Flag definitions */
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#define RQSFLAG_CONTINUATION 0x01
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#define RQSFLAG_FULL 0x02
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#define RQSFLAG_BADHEADER 0x04
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#define RQSFLAG_BADPACKET 0x08
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/* RQS entry_type definitions */
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#define RQSTYPE_REQUEST 1
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#define RQSTYPE_DATASEG 2
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#define RQSTYPE_RESPONSE 3
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#define RQSTYPE_MARKER 4
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#define RQSTYPE_CMDONLY 5
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#define ISP_RQDSEG 4
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typedef struct {
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isphdr_t req_header;
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u_int32_t req_handle;
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#if BYTE_ORDER == BIG_ENDIAN
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u_int8_t req_target;
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u_int8_t req_lun_trn;
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#else
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u_int8_t req_lun_trn;
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u_int8_t req_target;
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#endif
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u_int16_t req_cdblen;
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#define req_modifier req_cdblen /* marker packet */
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u_int16_t req_flags;
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u_int16_t _res1;
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u_int16_t req_time;
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u_int16_t req_seg_count;
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u_int8_t req_cdb[12];
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ispds_t req_dataseg[ISP_RQDSEG];
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} ispreq_t;
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/* req_flag values */
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#define REQFLAG_NODISCON 0x0001
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#define REQFLAG_HTAG 0x0002
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#define REQFLAG_OTAG 0x0004
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#define REQFLAG_STAG 0x0008
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#define REQFLAG_TARGET_RTN 0x0010
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#define REQFLAG_NODATA 0x0000
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#define REQFLAG_DATA_IN 0x0020
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#define REQFLAG_DATA_OUT 0x0040
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#define REQFLAG_DATA_UNKNOWN 0x0060
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#define REQFLAG_DISARQ 0x0100
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typedef struct {
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isphdr_t req_header;
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u_int32_t req_handle;
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#if BYTE_ORDER == BIG_ENDIAN
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u_int8_t req_target;
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u_int8_t req_lun_trn;
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#else
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u_int8_t req_lun_trn;
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u_int8_t req_target;
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#endif
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u_int16_t req_cdblen;
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u_int16_t req_flags;
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u_int16_t _res1;
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u_int16_t req_time;
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u_int16_t req_seg_count;
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u_int8_t req_cdb[44];
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} ispextreq_t;
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#define ISP_CDSEG 7
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typedef struct {
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isphdr_t req_header;
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u_int32_t _res1;
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ispds_t req_dataseg[ISP_CDSEG];
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} ispcontreq_t;
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typedef struct {
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isphdr_t req_header;
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u_int32_t _res1;
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#if BYTE_ORDER == BIG_ENDIAN
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u_int8_t req_target;
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u_int8_t req_lun_trn;
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u_int8_t _res2;
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u_int8_t req_modifier;
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#else
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u_int8_t req_lun_trn;
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u_int8_t req_target;
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u_int8_t req_modifier;
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u_int8_t _res2;
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#endif
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} ipsmarkreq_t;
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#define SYNC_DEVICE 0
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#define SYNC_TARGET 1
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#define SYNC_ALL 2
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typedef struct {
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isphdr_t req_header;
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u_int32_t req_handle;
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u_int16_t req_scsi_status;
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u_int16_t req_completion_status;
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u_int16_t req_state_flags;
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u_int16_t req_status_flags;
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u_int16_t req_time;
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u_int16_t req_sense_len;
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u_int32_t req_resid;
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u_int8_t _res1[8];
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u_int8_t req_sense_data[32];
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} ispstatusreq_t;
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#define RQCS_COMPLETE 0x0000
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#define RQCS_INCOMPLETE 0x0001
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#define RQCS_DMA_ERROR 0x0002
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#define RQCS_TRANSPORT_ERROR 0x0003
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#define RQCS_RESET_OCCURRED 0x0004
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#define RQCS_ABORTED 0x0005
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#define RQCS_TIMEOUT 0x0006
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#define RQCS_DATA_OVERRUN 0x0007
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#define RQCS_COMMAND_OVERRUN 0x0008
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#define RQCS_STATUS_OVERRUN 0x0009
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#define RQCS_BAD_MESSAGE 0x000a
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#define RQCS_NO_MESSAGE_OUT 0x000b
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#define RQCS_EXT_ID_FAILED 0x000c
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#define RQCS_IDE_MSG_FAILED 0x000d
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#define RQCS_ABORT_MSG_FAILED 0x000e
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#define RQCS_REJECT_MSG_FAILED 0x000f
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#define RQCS_NOP_MSG_FAILED 0x0010
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#define RQCS_PARITY_ERROR_MSG_FAILED 0x0011
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#define RQCS_DEVICE_RESET_MSG_FAILED 0x0012
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#define RQCS_ID_MSG_FAILED 0x0013
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#define RQCS_UNEXP_BUS_FREE 0x0014
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#define RQCS_DATA_UNDERRUN 0x0015
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#define RQSF_GOT_BUS 0x0100
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#define RQSF_GOT_TARGET 0x0200
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#define RQSF_SENT_CDB 0x0400
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#define RQSF_TRANFERRED_DATA 0x0800
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#define RQSF_GOT_STATUS 0x1000
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#define RQSF_GOT_SENSE 0x2000
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#define RQSTF_DISCONNECT 0x0001
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#define RQSTF_SYNCHRONOUS 0x0002
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#define RQSTF_PARITY_ERROR 0x0004
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#define RQSTF_BUS_RESET 0x0008
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#define RQSTF_DEVICE_RESET 0x0010
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#define RQSTF_ABORTED 0x0020
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#define RQSTF_TIMEOUT 0x0040
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#define RQSTF_NEGOTIATION 0x0080
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#endif /* _ISPMBOX_H */
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