306 lines
8.2 KiB
C
306 lines
8.2 KiB
C
/* $NetBSD: intr.c,v 1.27 1995/01/03 01:30:47 mycroft Exp $ */
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/*-
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* Copyright (c) 1993, 1994 Charles Hannum.
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)isa.c 7.2 (Berkeley) 5/13/91
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*/
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#include <sys/param.h>
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#include <sys/syslog.h>
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#include <sys/device.h>
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#include <machine/pio.h>
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#include <machine/cpufunc.h>
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#include <i386/isa/isareg.h>
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#include <i386/isa/isavar.h>
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#include <i386/isa/icu.h>
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#define IDTVEC(name) __CONCAT(X,name)
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/* default interrupt vector table entries */
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extern IDTVEC(wild), IDTVEC(intr)[], IDTVEC(fast)[];
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extern struct gate_descriptor idt[];
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/*
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* Fill in default interrupt table (in case of spuruious interrupt
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* during configuration of kernel, setup interrupt control unit
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*/
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void
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isa_defaultirq()
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{
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int i;
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imask[IPL_BIO] |= SIR_CLOCKMASK;
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imask[IPL_NET] |= SIR_NETMASK;
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imask[IPL_TTY] |= SIR_TTYMASK;
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imask[IPL_CLOCK] |= SIR_CLOCKMASK;
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/* icu vectors */
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for (i = 0; i < ICU_LEN; i++)
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setgate(&idt[ICU_OFFSET + i], IDTVEC(intr)[i], 0, SDT_SYS386IGT,
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SEL_KPL);
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/* initialize 8259's */
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outb(IO_ICU1, 0x11); /* reset; program device, four bytes */
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outb(IO_ICU1+1, ICU_OFFSET); /* starting at this vector index */
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outb(IO_ICU1+1, 1 << IRQ_SLAVE); /* slave on line 2 */
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#ifdef AUTO_EOI_1
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outb(IO_ICU1+1, 2 | 1); /* auto EOI, 8086 mode */
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#else
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outb(IO_ICU1+1, 1); /* 8086 mode */
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#endif
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outb(IO_ICU1+1, 0xff); /* leave interrupts masked */
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outb(IO_ICU1, 0x68); /* special mask mode (if available) */
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outb(IO_ICU1, 0x0a); /* Read IRR by default. */
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#ifdef REORDER_IRQ
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outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */
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#endif
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outb(IO_ICU2, 0x11); /* reset; program device, four bytes */
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outb(IO_ICU2+1, ICU_OFFSET+8); /* staring at this vector index */
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outb(IO_ICU2+1, IRQ_SLAVE);
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#ifdef AUTO_EOI_2
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outb(IO_ICU2+1, 2 | 1); /* auto EOI, 8086 mode */
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#else
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outb(IO_ICU2+1, 1); /* 8086 mode */
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#endif
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outb(IO_ICU2+1, 0xff); /* leave interrupts masked */
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outb(IO_ICU2, 0x68); /* special mask mode (if available) */
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outb(IO_ICU2, 0x0a); /* Read IRR by default. */
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}
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/*
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* Handle a NMI, possibly a machine check.
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* return true to panic system, false to ignore.
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*/
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int
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isa_nmi()
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{
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log(LOG_CRIT, "NMI port 61 %x, port 70 %x\n", inb(0x61), inb(0x70));
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return(0);
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}
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/*
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* Caught a stray interrupt, notify
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*/
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void
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isa_strayintr(irq)
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int irq;
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{
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static u_long strays;
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/*
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* Stray interrupts on irq 7 occur when an interrupt line is raised
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* and then lowered before the CPU acknowledges it. This generally
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* means either the device is screwed or something is cli'ing too
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* long and it's timing out.
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*/
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if (++strays <= 5)
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log(LOG_ERR, "stray interrupt %d%s\n", irq,
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strays >= 5 ? "; stopped logging" : "");
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}
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int fastvec;
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int intrtype[ICU_LEN], intrmask[ICU_LEN], intrlevel[ICU_LEN];
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struct intrhand *intrhand[ICU_LEN];
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/*
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* Recalculate the interrupt masks from scratch.
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* We could code special registry and deregistry versions of this function that
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* would be faster, but the code would be nastier, and we don't expect this to
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* happen very much anyway.
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*/
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void
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intr_calculatemasks()
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{
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int irq, level;
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struct intrhand *q;
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/* First, figure out which levels each IRQ uses. */
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for (irq = 0; irq < ICU_LEN; irq++) {
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register int levels = 0;
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for (q = intrhand[irq]; q; q = q->ih_next)
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if (q->ih_level != IPL_NONE)
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levels |= 1 << q->ih_level;
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intrlevel[irq] = levels;
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}
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/* Then figure out which IRQs use each level. */
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for (level = 0; level < 4; level++) {
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register int irqs = 0;
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for (irq = 0; irq < ICU_LEN; irq++)
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if (intrlevel[irq] & (1 << level))
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irqs |= 1 << irq;
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/* Preserve any softintr dependencies we set up earlier. */
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imask[level] = (imask[level] & -(1 << ICU_LEN)) | irqs;
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}
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#include "sl.h"
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#include "ppp.h"
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#if NSL > 0 || NPPP > 0
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/* In the presence of SLIP or PPP, splimp > spltty. */
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imask[IPL_NET] |= imask[IPL_TTY];
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#endif
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/* And eventually calculate the complete masks. */
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for (irq = 0; irq < ICU_LEN; irq++) {
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register int irqs = 1 << irq;
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for (q = intrhand[irq]; q; q = q->ih_next)
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if (q->ih_level != IPL_NONE)
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irqs |= imask[q->ih_level];
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intrmask[irq] = irqs;
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}
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/* Lastly, determine which IRQs are actually in use. */
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{
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register int irqs = 0;
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for (irq = 0; irq < ICU_LEN; irq++)
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if (intrhand[irq])
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irqs |= 1 << irq;
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if (irqs >= 0x100) /* any IRQs >= 8 in use */
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irqs |= 1 << IRQ_SLAVE;
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imen = ~irqs;
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SET_ICUS();
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}
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}
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int
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fakeintr(arg)
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void *arg;
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{
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return 0;
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}
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/*
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* Set up an interrupt handler to start being called.
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*/
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void
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intr_establish(irq, type, ih)
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int irq, type;
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struct intrhand *ih;
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{
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int mask;
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struct intrhand **p, *q;
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static struct intrhand fakehand = {fakeintr};
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static char *typename[] = {NULL, "pulsed", "edge-triggered",
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"level-triggered"};
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mask = 1 << irq;
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if (irq < 0 || irq > ICU_LEN || type == IST_NONE)
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panic("intr_establish: bogus irq");
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if (fastvec & mask)
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panic("intr_establish: irq is already fast vector");
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switch (intrtype[irq]) {
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case IST_NONE:
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intrtype[irq] = type;
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break;
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case IST_EDGE:
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case IST_LEVEL:
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if (type == intrtype[irq])
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break;
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case IST_PULSE:
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if (type != IST_NONE)
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panic("intr_establish: can't share %s with %s",
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typename[intrtype[irq]], typename[type]);
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break;
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}
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/*
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* Figure out where to put the handler.
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* This is O(N^2), but we want to preserve the order, and N is
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* generally small.
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*/
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for (p = &intrhand[irq]; (q = *p) != NULL; p = &q->ih_next)
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;
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/*
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* Actually install a fake handler momentarily, since we might be doing
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* this with interrupts enabled and don't want the real routine called
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* until masking is set up.
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*/
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fakehand.ih_level = ih->ih_level;
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*p = &fakehand;
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intr_calculatemasks();
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/*
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* Poke the real handler in now.
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*/
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ih->ih_count = 0;
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ih->ih_next = NULL;
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*p = ih;
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}
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/*
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* Deregister an interrupt handler.
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*/
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void
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intr_disestablish(irq, ih)
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int irq;
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struct intrhand *ih;
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{
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int mask;
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struct intrhand **p, *q;
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mask = 1 << irq;
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if (irq < 0 || irq > ICU_LEN)
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panic("intr_disestablish: bogus irq");
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if (fastvec & mask)
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fastvec &= ~mask;
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/*
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* Remove the handler from the chain.
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* This is O(n^2), too.
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*/
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for (p = &intrhand[irq]; (q = *p) != NULL && q != ih; p = &q->ih_next)
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;
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if (q)
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*p = q->ih_next;
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else
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panic("intr_disestablish: handler not registered");
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intr_calculatemasks();
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if (intrhand[irq] == NULL)
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intrtype[irq] = IST_NONE;
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}
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