512 lines
10 KiB
NASM
512 lines
10 KiB
NASM
; $NetBSD: arm.asm,v 1.2 2001/03/23 08:48:12 toshii Exp $
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;
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; Copyright (c) 2001 The NetBSD Foundation, Inc.
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; All rights reserved.
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;
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; This code is derived from software contributed to The NetBSD Foundation
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; by UCHIYAMA Yasushi.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; 1. Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; 2. Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the distribution.
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; 3. All advertising materials mentioning features or use of this software
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; must display the following acknowledgement:
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; This product includes software developed by the NetBSD
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; Foundation, Inc. and its contributors.
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; 4. Neither the name of The NetBSD Foundation nor the names of its
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; contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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; ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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; BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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; POSSIBILITY OF SUCH DAMAGE.
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;
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;
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;armasm.exe $(InputPath)
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;arm.obj
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;
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; dummy buffer for WritebackDCache
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EXPORT |dcachebuf| [DATA]
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AREA |.data|, DATA
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|dcachebuf|
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% 8192 ; D-cache size
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AREA |.text|, CODE, PIC
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;
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; Operation mode ops.
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;
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EXPORT |SetSVCMode|
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|SetSVCMode| PROC
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mrs r0, cpsr
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bic r0, r0, #0x1f
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orr r0, r0, #0x13
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msr cpsr, r0
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mov pc, lr
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ENDP ; |SetSVCMode|
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EXPORT |SetSystemMode|
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|SetSystemMode| PROC
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mrs r0, cpsr
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orr r0, r0, #0x1f
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msr cpsr, r0
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mov pc, lr
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ENDP ; |SetSystemMode|
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;
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; Interrupt ops.
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;
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EXPORT |DI|
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|DI| PROC
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mrs r0, cpsr
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orr r0, r0, #0xc0
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msr cpsr, r0
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mov pc, lr
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ENDP ; |DI|
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EXPORT |EI|
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|EI| PROC
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mrs r0, cpsr
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bic r0, r0, #0xc0
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msr cpsr, r0
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mov pc, lr
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ENDP ; |EI|
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;
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; Cache ops.
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;
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EXPORT |InvalidateICache|
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|InvalidateICache| PROC
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; c7 (CRn) Cache Control Register
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; c5, 0 (CRm, opcode_2) Flush I
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; r0 (Rd) ignored
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mcr p15, 0, r0, c7, c5, 0
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mov pc, lr
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ENDP ; |InvalidateICache|
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EXPORT |WritebackDCache|
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|WritebackDCache| PROC
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ldr r0, [pc, #16] ; dcachebuf
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add r1, r0, #8192 ; cache-size is 8Kbyte.
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|wbdc1|
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ldr r2, [r0], #32 ; line-size is 32byte.
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teq r1, r0
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bne |wbdc1|
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mov pc, lr
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DCD |dcachebuf|
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ENDP ; |WritebackDCache|
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EXPORT |InvalidateDCache|
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|InvalidateDCache| PROC
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; c7 (CRn) Cache Control Register
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; c6, 0 (CRm, opcode_2) Flush D
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; r0 (Rd) ignored
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mcr p15, 0, r0, c7, c6, 0
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mov pc, lr
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ENDP ; |InvalidateDCache|
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EXPORT |WritebackInvalidateDCache|
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|WritebackInvalidateDCache| PROC
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ldr r0, [pc, #20] ; dcachebuf
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add r1, r0, #8192
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|wbidc1|
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ldr r2, [r0], #32
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teq r1, r0
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bne |wbidc1|
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mcr p15, 0, r0, c7, c6, 0
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mov pc, lr
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DCD |dcachebuf|
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ENDP ; |WritebackInvalidateDCache|
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;
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; WriteBuffer ops
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;
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EXPORT |WritebufferFlush|
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|WritebufferFlush| PROC
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; c7 (CRn) Cache Control Register
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; c10, 4(CRm, opcode_2) Flush D
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; r0 (Rd) ignored
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mcr p15, 0, r0, c7, c10, 4
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mov pc, lr
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ENDP ; |WritebufferFlush|
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;
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; TLB ops.
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;
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EXPORT |FlushIDTLB|
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|FlushIDTLB| PROC
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mcr p15, 0, r0, c8, c7, 0
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mov pc, lr
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ENDP ; |FlushIDTLB|
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EXPORT |FlushITLB|
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|FlushITLB| PROC
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mcr p15, 0, r0, c8, c5, 0
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mov pc, lr
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ENDP ; |FlushITLB|
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EXPORT |FlushDTLB|
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|FlushDTLB| PROC
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mcr p15, 0, r0, c8, c6, 0
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mov pc, lr
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ENDP ; |FlushITLB|
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EXPORT |FlushDTLBS|
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|FlushDTLBS| PROC
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mcr p15, 0, r0, c8, c6, 1
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mov pc, lr
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ENDP ; |FlushITLBS|
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;
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; CurrentProgramStatusRegister access.
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;
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EXPORT |GetCPSR|
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|GetCPSR| PROC
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mrs r0, cpsr
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mov pc, lr
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ENDP ; |GetCPSR|
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EXPORT |SetCPSR|
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|SetCPSR| PROC
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msr cpsr, r0
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mov pc, lr
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ENDP ; |SetCPSR|
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;
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; SA-1100 Coprocessor15 access.
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;
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; Reg0 ID (R)
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EXPORT |GetCop15Reg0|
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|GetCop15Reg0| PROC
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mrc p15, 0, r0, c0, c0, 0
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; 0x4401a119 (44|01 = version 4|A11 = SA1100|9 = E stepping)
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mov pc, lr
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ENDP ; |GetCop15Reg0|
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; Reg1 Control (R/W)
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EXPORT |GetCop15Reg1|
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|GetCop15Reg1| PROC
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mrc p15, 0, r0, c1, c0, 0
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; 0xc007327f (||...........|||..||..|..|||||||)
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; 0 (1)MMU enabled
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; 1 (1)Address fault enabled
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; 2 (1)D-cache enabled
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; 3 (1)Write-buffer enabled
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; 7 (0)little-endian
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; 8 (0)MMU protection (System)
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; 9 (1)MMU protection (ROM)
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; 12 (1)I-cache enabled
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; 13 (1)Base address of interrupt vector is 0xffff0000
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mov pc, lr
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ENDP ; |GetCop15Reg1|
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EXPORT |SetCop15Reg1|
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|SetCop15Reg1| PROC
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mcr p15, 0, r0, c1, c0, 0
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nop
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nop
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nop
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mov pc, lr
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ENDP ; |SetCop15Reg1|
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; Reg2 Translation table base (R/W)
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EXPORT |GetCop15Reg2|
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|GetCop15Reg2| PROC
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mrc p15, 0, r0, c2, c0, 0
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mov pc, lr
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ENDP ; |GetCop15Reg2|
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EXPORT |SetCop15Reg2|
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|SetCop15Reg2| PROC
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mcr p15, 0, r0, c2, c0, 0
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mov pc, lr
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ENDP ; |SetCop15Reg2|
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; Reg3 Domain access control (R/W)
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EXPORT |GetCop15Reg3|
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|GetCop15Reg3| PROC
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mrc p15, 0, r0, c3, c0, 0
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mov pc, lr
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ENDP ; |GetCop15Reg3|
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EXPORT |SetCop15Reg3|
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|SetCop15Reg3| PROC
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mcr p15, 0, r0, c3, c0, 0
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mov pc, lr
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ENDP ; |SetCop15Reg3|
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; Reg5 Fault status (R/W)
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EXPORT |GetCop15Reg5|
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|GetCop15Reg5| PROC
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mrc p15, 0, r0, c5, c0, 0
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mov pc, lr
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ENDP ; |GetCop15Reg5|
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; Reg6 Fault address (R/W)
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EXPORT |GetCop15Reg6|
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|GetCop15Reg6| PROC
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mrc p15, 0, r0, c6, c0, 0
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mov pc, lr
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ENDP ; |GetCop15Reg6|
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; Reg7 Cache operations (W)
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; -> Cache ops
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; Reg8 TLB operations (Flush) (W)
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; -> TLB ops
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; Reg9 Read buffer operations (W)
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; Reg13 Process ID (R/W)
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EXPORT |GetCop15Reg13|
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|GetCop15Reg13| PROC
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mrc p15, 0, r0, c13, c0, 0
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mov pc, lr
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ENDP ; |GetCop15Reg13|
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EXPORT |SetCop15Reg13|
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|SetCop15Reg13| PROC
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mcr p15, 0, r0, c13, c0, 0
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mov pc, lr
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ENDP ; |SetCop15Reg13|
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; Reg14 Breakpoint (R/W)
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EXPORT |GetCop15Reg14|
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|GetCop15Reg14| PROC
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mrc p15, 0, r0, c14, c0, 0
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mov pc, lr
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ENDP ; |GetCop15Reg14|
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; Reg15 Test, clock, and idle (W)
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; FlatJump (kaddr_t bootinfo, kaddr_t pvec, kaddr_t stack
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; kaddr_t jump)
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; bootinfo boot infomation block address.
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; pvec page vector of kernel.
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; stack physical address of stack
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; jump physical address of boot function
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; *** MMU and pipeline behavier are SA-1100 specific. ***
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EXPORT |FlatJump|
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|FlatJump| PROC
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; disable interrupt
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mrs r4, cpsr
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orr r4, r4, #0xc0
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msr cpsr, r4
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; disable MMU, I/D-Cache, Writebuffer.
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; interrupt vector address is 0xffff0000
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; 32bit exception handler/address range.
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ldr r4, [pc, #24]
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; Disable WB/Cache/MMU
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mcr p15, 0, r4, c1, c0, 0
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; Invalidate I/D-cache.
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mcr p15, 0, r4, c7, c7, 0 ; Fetch translated fetch
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; Invalidate TLB entries.
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mcr p15, 0, r4, c8, c7, 0 ; Fetch translated decode
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; jump to kernel entry physical address.
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mov pc, r3 ; Fetch translated execute
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; NOTREACHED
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nop ; Fetch nontranslated cache access
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nop ; Fetch nontranslated writeback
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mov pc, lr ; Fetch nontranslated
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DCD 0x00002030
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ENDP ; |FlatJump|
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;
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; UART test
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;
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; boot_func (u_int32_t mapaddr, u_int32_t bootinfo, u_int32_t flags)
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;
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EXPORT |boot_func|
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|boot_func| PROC
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nop ; Cop15 hazard
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nop ; Cop15 hazard
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nop ; Cop15 hazard
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mov sp, r2 ; set bootloader stack
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; mov r4, r0
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; mov r5, r1
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; bl colorbar
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; mov r0, r4
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; mov r1, r5
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bl boot
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nop ; NOTREACHED
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nop
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ENDP ; |boot_func|
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EXPORT |colorbar|
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|colorbar| PROC
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stmea sp!, {r4-r7, lr}
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adr r4, |$FBADDR|
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ldr r4, [r4]
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mov r7, #8
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add r0, r0, r7
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|color_loop|
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mov r6, r0
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and r6, r6, #7
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orr r6, r6, r6, LSL #8
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orr r6, r6, r6, LSL #16
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add r5, r4, #0x9600
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|fb_loop|
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str r6, [r4], #4
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cmp r4, r5
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blt |fb_loop|
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subs r7, r7, #1
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bne |color_loop|
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ldmea sp!, {r4-r7, pc}
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|$FBADDR|
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DCD 0xc0003000 ; use WindowsCE default.
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ENDP ; |colorbar|
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EXPORT |boot|
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|boot| PROC
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;
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; UART test code
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;
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; ; print boot_info address (r0) and page_vector start address (r1).
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; mov r4, r0
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; mov r5, r1
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; mov r0, #'I'
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; bl btputc
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; mov r0, r4
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; bl hexdump
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; mov r0, #'P'
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; bl btputc
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; mov r0, r5
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; bl hexdump
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; mov r7, r4
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; mov r2, r5 ; start
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mov r7, r0 ; if enabled above debug print, remove this.
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mov r2, r1 ; if enabled above debug print, remove this.
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|page_loop|
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mvn r0, #0 ; ~0
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cmp r2, r0
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beq |page_end| ; if (next == ~0) goto page_end
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mov r1, r2 ; p = next
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ldr r2, [r1] ; next
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ldr r3, [r1, #4] ; src
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ldr r4, [r1, #8] ; dst
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ldr r5, [r1, #12] ; sz
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cmp r3, r0
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add r6, r4, r5 ; end address
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bne |page_memcpy4| ; if (src != ~0) goto page_memcpy4
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mov r0, #0
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|page_memset| ; memset (dst, 0, sz) uncached.
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str r0, [r4], #4
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cmp r4, r6
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blt |page_memset|
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b |page_loop|
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|page_memcpy4| ; memcpy (dst, src, sz) uncached.
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ldr r0, [r3], #4
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ldr r5, [r3], #4
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str r0, [r4], #4
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cmp r4, r6
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strlt r5, [r4], #4
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cmplt r4, r6
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blt |page_memcpy4|
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b |page_loop|
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|page_end|
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;
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; jump to kernel
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;
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; mov r0, #'E'
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; bl btputc
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; ldr r0, [r7]
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; bl hexdump
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; ldr r0, [r7]
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; ldr r0, [r0]
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; bl hexdump
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; set stack pointer
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mov r5, #4096
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add r6, r6, #8192
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sub r5, r5, #1
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bic sp, r6, r5
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; set bootargs
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ldr r4, [r7]
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ldr r0, [r7, #4]
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ldr r1, [r7, #8]
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ldr r2, [r7, #12]
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mov pc, r4
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; NOTREACHED
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|infinite_loop|
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nop
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nop
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nop
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nop
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nop
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b |infinite_loop|
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ENDP ; |boot|
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|btputc| PROC
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adr r1, |$UARTTXBSY|
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ldr r1, [r1]
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|btputc_busy|
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ldr r2, [r1]
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and r2, r2, #1
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cmp r2, #1
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beq |btputc_busy|
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adr r1, |$UARTTXADR|
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ldr r1, [r1]
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str r0, [r1]
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mov pc, lr
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ENDP ;|btputc|
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|hexdump| PROC
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stmea sp!, {r4-r5, lr}
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mov r4, r0
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mov r0, #0x30
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bl btputc
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mov r0, #0x78
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bl btputc
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mov r0, r4
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; Transmit register address
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adr r1, |$UARTTXADR|
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ldr r1, [r1]
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; Transmit busy register address
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adr r2, |$UARTTXBSY|
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ldr r2, [r2]
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mov r5, #8
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|hex_loop|
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mov r3, r0, LSR #28
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cmp r3, #9
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addgt r3, r3, #0x41 - 10
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addle r3, r3, #0x30
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|hex_busyloop|
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ldr r4, [r2]
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and r4, r4, #1
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cmp r4, #1
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beq |hex_busyloop|
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str r3, [r1]
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mov r0, r0, LSL #4
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subs r5, r5, #1
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bne |hex_loop|
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mov r0, #0x0d
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bl btputc
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mov r0, #0x0a
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bl btputc
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ldmea sp!, {r4-r5, pc}
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ENDP ;|hexdump|
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|$UARTTXADR|
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DCD 0x80050014
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|$UARTTXBSY|
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DCD 0x80050020
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EXPORT |boot_func_end| [ DATA ]
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|boot_func_end| DCD 0x0
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END
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