498 lines
13 KiB
C
498 lines
13 KiB
C
/* $NetBSD: cbiisc.c,v 1.9 1999/09/30 22:59:52 thorpej Exp $ */
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/*
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* Copyright (c) 1997 Michael L. Hitch
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* Copyright (c) 1982, 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product contains software written by Michael L. Hitch for
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* the NetBSD project.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/errno.h>
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#include <sys/ioctl.h>
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#include <sys/device.h>
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#include <sys/buf.h>
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#include <sys/proc.h>
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#include <sys/user.h>
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#include <sys/queue.h>
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#include <dev/scsipi/scsi_all.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <dev/scsipi/scsi_message.h>
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#include <machine/cpu.h>
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#include <machine/param.h>
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#include <dev/ic/ncr53c9xreg.h>
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#include <dev/ic/ncr53c9xvar.h>
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#include <amiga/amiga/isr.h>
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#include <amiga/dev/cbiiscvar.h>
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#include <amiga/dev/zbusvar.h>
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void cbiiscattach __P((struct device *, struct device *, void *));
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int cbiiscmatch __P((struct device *, struct cfdata *, void *));
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/* Linkup to the rest of the kernel */
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struct cfattach cbiisc_ca = {
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sizeof(struct cbiisc_softc), cbiiscmatch, cbiiscattach
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};
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struct scsipi_device cbiisc_dev = {
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NULL, /* Use default error handler */
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NULL, /* have a queue, served by this */
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NULL, /* have no async handler */
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NULL, /* Use default 'done' routine */
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};
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/*
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* Functions and the switch for the MI code.
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*/
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u_char cbiisc_read_reg __P((struct ncr53c9x_softc *, int));
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void cbiisc_write_reg __P((struct ncr53c9x_softc *, int, u_char));
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int cbiisc_dma_isintr __P((struct ncr53c9x_softc *));
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void cbiisc_dma_reset __P((struct ncr53c9x_softc *));
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int cbiisc_dma_intr __P((struct ncr53c9x_softc *));
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int cbiisc_dma_setup __P((struct ncr53c9x_softc *, caddr_t *,
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size_t *, int, size_t *));
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void cbiisc_dma_go __P((struct ncr53c9x_softc *));
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void cbiisc_dma_stop __P((struct ncr53c9x_softc *));
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int cbiisc_dma_isactive __P((struct ncr53c9x_softc *));
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struct ncr53c9x_glue cbiisc_glue = {
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cbiisc_read_reg,
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cbiisc_write_reg,
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cbiisc_dma_isintr,
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cbiisc_dma_reset,
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cbiisc_dma_intr,
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cbiisc_dma_setup,
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cbiisc_dma_go,
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cbiisc_dma_stop,
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cbiisc_dma_isactive,
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0,
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};
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/* Maximum DMA transfer length to reduce impact on high-speed serial input */
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u_long cbiisc_max_dma = 1024;
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extern int ser_open_speed;
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u_long cbiisc_cnt_pio = 0; /* number of PIO transfers */
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u_long cbiisc_cnt_dma = 0; /* number of DMA transfers */
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u_long cbiisc_cnt_dma2 = 0; /* number of DMA transfers broken up */
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u_long cbiisc_cnt_dma3 = 0; /* number of pages combined */
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#ifdef DEBUG
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struct {
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u_char hardbits;
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u_char status;
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u_char xx;
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u_char yy;
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} cbiisc_trace[128];
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int cbiisc_trace_ptr = 0;
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int cbiisc_trace_enable = 1;
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void cbiisc_dump __P((void));
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#endif
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/*
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* if we are a Phase5 CyberSCSI II
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*/
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int
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cbiiscmatch(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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struct zbus_args *zap;
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volatile u_char *regs;
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zap = aux;
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if (zap->manid != 0x2140 || zap->prodid != 25)
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return(0);
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regs = &((volatile u_char *)zap->va)[0x1ff03];
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if (badaddr((caddr_t)regs))
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return(0);
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regs[NCR_CFG1 * 4] = 0;
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regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7;
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delay(5);
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if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7))
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return(0);
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return(1);
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}
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/*
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* Attach this instance, and then all the sub-devices
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*/
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void
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cbiiscattach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct cbiisc_softc *csc = (void *)self;
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struct ncr53c9x_softc *sc = &csc->sc_ncr53c9x;
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struct zbus_args *zap;
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extern u_long scsi_nosync;
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extern int shift_nosync;
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extern int ncr53c9x_debug;
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/*
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* Set up the glue for MI code early; we use some of it here.
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*/
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sc->sc_glue = &cbiisc_glue;
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/*
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* Save the regs
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*/
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zap = aux;
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csc->sc_reg = &((volatile u_char *)zap->va)[0x1ff03];
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csc->sc_dmabase = &csc->sc_reg[0x80];
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sc->sc_freq = 40; /* Clocked at 40Mhz */
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printf(": address %p", csc->sc_reg);
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sc->sc_id = 7;
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/*
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* It is necessary to try to load the 2nd config register here,
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* to find out what rev the FAS chip is, else the ncr53c9x_reset
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* will not set up the defaults correctly.
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*/
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sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
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sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE;
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sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB;
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sc->sc_rev = NCR_VARIANT_FAS216;
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/*
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* This is the value used to start sync negotiations
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* Note that the NCR register "SYNCTP" is programmed
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* in "clocks per byte", and has a minimum value of 4.
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* The SCSI period used in negotiation is one-fourth
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* of the time (in nanoseconds) needed to transfer one byte.
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* Since the chip's clock is given in MHz, we have the following
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* formula: 4 * period = (1000 / freq) * 4
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*/
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sc->sc_minsync = 1000 / sc->sc_freq;
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/*
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* get flags from -I argument and set cf_flags.
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* NOTE: low 8 bits are to disable disconnect, and the next
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* 8 bits are to disable sync.
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*/
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sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync)
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& 0xffff;
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shift_nosync += 16;
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/* Use next 16 bits of -I argument to set ncr53c9x_debug flags */
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ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff;
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shift_nosync += 16;
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#if 1
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if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00)
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sc->sc_minsync = 0;
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#endif
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/* Really no limit, but since we want to fit into the TCR... */
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sc->sc_maxxfer = 64 * 1024;
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/*
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* Configure interrupts.
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*/
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csc->sc_isr.isr_intr = (int (*)(void *))ncr53c9x_intr;
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csc->sc_isr.isr_arg = sc;
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csc->sc_isr.isr_ipl = 2;
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add_isr(&csc->sc_isr);
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/*
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* Now try to attach all the sub-devices
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*/
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sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd;
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sc->sc_adapter.scsipi_minphys = minphys;
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ncr53c9x_attach(sc, &cbiisc_dev);
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}
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/*
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* Glue functions.
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*/
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u_char
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cbiisc_read_reg(sc, reg)
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struct ncr53c9x_softc *sc;
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int reg;
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{
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struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
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return csc->sc_reg[reg * 4];
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}
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void
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cbiisc_write_reg(sc, reg, val)
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struct ncr53c9x_softc *sc;
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int reg;
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u_char val;
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{
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struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
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u_char v = val;
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csc->sc_reg[reg * 4] = v;
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#ifdef DEBUG
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if (cbiisc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ &&
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reg == NCR_CMD/* && csc->sc_active*/) {
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cbiisc_trace[(cbiisc_trace_ptr - 1) & 127].yy = v;
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/* printf(" cmd %x", v);*/
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}
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#endif
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}
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int
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cbiisc_dma_isintr(sc)
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struct ncr53c9x_softc *sc;
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{
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struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
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if ((csc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0)
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return 0;
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if (sc->sc_state == NCR_CONNECTED)
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csc->sc_reg[0x40] = CBIISC_PB_LED;
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else
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csc->sc_reg[0x40] = 0;
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#ifdef DEBUG
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if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ cbiisc_trace_enable) {
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cbiisc_trace[cbiisc_trace_ptr].status = csc->sc_reg[NCR_STAT * 4];
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cbiisc_trace[cbiisc_trace_ptr].xx = csc->sc_reg[NCR_CMD * 4];
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cbiisc_trace[cbiisc_trace_ptr].yy = csc->sc_active;
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cbiisc_trace_ptr = (cbiisc_trace_ptr + 1) & 127;
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}
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#endif
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return 1;
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}
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void
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cbiisc_dma_reset(sc)
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struct ncr53c9x_softc *sc;
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{
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struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
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csc->sc_active = 0;
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}
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int
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cbiisc_dma_intr(sc)
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struct ncr53c9x_softc *sc;
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{
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register struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
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register int cnt;
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NCR_DMA(("cbiisc_dma_intr: cnt %d int %x stat %x fifo %d ",
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csc->sc_dmasize, sc->sc_espintr, sc->sc_espstat,
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csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF));
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if (csc->sc_active == 0) {
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printf("cbiisc_intr--inactive DMA\n");
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return -1;
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}
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/* update sc_dmaaddr and sc_pdmalen */
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cnt = csc->sc_reg[NCR_TCL * 4];
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cnt += csc->sc_reg[NCR_TCM * 4] << 8;
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cnt += csc->sc_reg[NCR_TCH * 4] << 16;
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if (!csc->sc_datain) {
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cnt += csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF;
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csc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH;
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}
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cnt = csc->sc_dmasize - cnt; /* number of bytes transferred */
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NCR_DMA(("DMA xferred %d\n", cnt));
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if (csc->sc_xfr_align) {
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bcopy(csc->sc_alignbuf, *csc->sc_dmaaddr, cnt);
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csc->sc_xfr_align = 0;
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}
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*csc->sc_dmaaddr += cnt;
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*csc->sc_pdmalen -= cnt;
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csc->sc_active = 0;
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return 0;
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}
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int
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cbiisc_dma_setup(sc, addr, len, datain, dmasize)
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struct ncr53c9x_softc *sc;
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caddr_t *addr;
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size_t *len;
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int datain;
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size_t *dmasize;
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{
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struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
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paddr_t pa;
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u_char *ptr;
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size_t xfer;
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csc->sc_dmaaddr = addr;
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csc->sc_pdmalen = len;
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csc->sc_datain = datain;
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csc->sc_dmasize = *dmasize;
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/*
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* DMA can be nasty for high-speed serial input, so limit the
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* size of this DMA operation if the serial port is running at
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* a high speed (higher than 19200 for now - should be adjusted
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* based on cpu type and speed?).
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* XXX - add serial speed check XXX
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*/
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if (ser_open_speed > 19200 && cbiisc_max_dma != 0 &&
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csc->sc_dmasize > cbiisc_max_dma)
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csc->sc_dmasize = cbiisc_max_dma;
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ptr = *addr; /* Kernel virtual address */
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pa = kvtop(ptr); /* Physical address of DMA */
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xfer = min(csc->sc_dmasize, NBPG - (pa & (NBPG - 1)));
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csc->sc_xfr_align = 0;
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/*
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* If output and unaligned, stuff odd byte into FIFO
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*/
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if (datain == 0 && (int)ptr & 1) {
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NCR_DMA(("cbiisc_dma_setup: align byte written to fifo\n"));
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pa++;
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xfer--; /* XXXX CHECK THIS !!!! XXXX */
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csc->sc_reg[NCR_FIFO * 4] = *ptr++;
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}
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/*
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* If unaligned address, read unaligned bytes into alignment buffer
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*/
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else if ((int)ptr & 1) {
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pa = kvtop((caddr_t)&csc->sc_alignbuf);
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xfer = csc->sc_dmasize = min(xfer, sizeof (csc->sc_alignbuf));
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NCR_DMA(("cbiisc_dma_setup: align read by %d bytes\n", xfer));
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csc->sc_xfr_align = 1;
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}
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++cbiisc_cnt_dma; /* number of DMA operations */
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while (xfer < csc->sc_dmasize) {
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if ((pa + xfer) != kvtop(*addr + xfer))
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break;
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if ((csc->sc_dmasize - xfer) < NBPG)
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xfer = csc->sc_dmasize;
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else
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xfer += NBPG;
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++cbiisc_cnt_dma3;
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}
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if (xfer != *len)
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++cbiisc_cnt_dma2;
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csc->sc_dmasize = xfer;
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*dmasize = csc->sc_dmasize;
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csc->sc_pa = pa;
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#if defined(M68040) || defined(M68060)
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if (mmutype == MMU_68040) {
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if (csc->sc_xfr_align) {
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dma_cachectl(csc->sc_alignbuf,
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sizeof(csc->sc_alignbuf));
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}
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else
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dma_cachectl(*csc->sc_dmaaddr, csc->sc_dmasize);
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}
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#endif
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if (csc->sc_datain)
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pa &= ~1;
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else
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pa |= 1;
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csc->sc_dmabase[0] = (u_int8_t)(pa >> 24);
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csc->sc_dmabase[4] = (u_int8_t)(pa >> 16);
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csc->sc_dmabase[8] = (u_int8_t)(pa >> 8);
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csc->sc_dmabase[12] = (u_int8_t)(pa);
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csc->sc_active = 1;
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return 0;
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}
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void
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cbiisc_dma_go(sc)
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struct ncr53c9x_softc *sc;
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{
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}
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void
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cbiisc_dma_stop(sc)
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struct ncr53c9x_softc *sc;
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{
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}
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int
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cbiisc_dma_isactive(sc)
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struct ncr53c9x_softc *sc;
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{
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struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
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return csc->sc_active;
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}
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#ifdef DEBUG
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void
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cbiisc_dump()
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{
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int i;
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i = cbiisc_trace_ptr;
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printf("cbiisc_trace dump: ptr %x\n", cbiisc_trace_ptr);
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do {
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if (cbiisc_trace[i].hardbits == 0) {
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i = (i + 1) & 127;
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continue;
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}
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printf("%02x%02x%02x%02x(", cbiisc_trace[i].hardbits,
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cbiisc_trace[i].status, cbiisc_trace[i].xx, cbiisc_trace[i].yy);
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|
if (cbiisc_trace[i].status & NCRSTAT_INT)
|
|
printf("NCRINT/");
|
|
if (cbiisc_trace[i].status & NCRSTAT_TC)
|
|
printf("NCRTC/");
|
|
switch(cbiisc_trace[i].status & NCRSTAT_PHASE) {
|
|
case 0:
|
|
printf("dataout"); break;
|
|
case 1:
|
|
printf("datain"); break;
|
|
case 2:
|
|
printf("cmdout"); break;
|
|
case 3:
|
|
printf("status"); break;
|
|
case 6:
|
|
printf("msgout"); break;
|
|
case 7:
|
|
printf("msgin"); break;
|
|
default:
|
|
printf("phase%d?", cbiisc_trace[i].status & NCRSTAT_PHASE);
|
|
}
|
|
printf(") ");
|
|
i = (i + 1) & 127;
|
|
} while (i != cbiisc_trace_ptr);
|
|
printf("\n");
|
|
}
|
|
#endif
|