72 lines
2.9 KiB
C
72 lines
2.9 KiB
C
/* $NetBSD: iocc.h,v 1.2 2008/04/28 20:23:34 martin Exp $ */
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/*-
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* Copyright (c) 2007 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Tim Rightnour
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _RS6000_IOCC_H_
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#define _RS6000_IOCC_H_
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/*
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* Ports and defines used for control of the IOCC
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*/
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/* MCA register addresses for PPC */
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#define IOCC_BASE_PPC 0x10000
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#define IOCC_POSBASE_PPC 0x400000
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#define IOCC_BASE IOCC_BASE_PPC
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#define IOCC_POSBASE IOCC_POSBASE_PPC
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#define IOCC_CFG_REG (IOCC_BASE + 0x80) /* config reg */
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#define IOCC_PERS (IOCC_BASE + 0x88) /* personalization */
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#define IOCC_TCE_ADDR_HIGH (IOCC_BASE + 0x98) /* MSW of tceaddr */
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#define IOCC_TCE_ADDR_LOW (IOCC_BASE + 0x9C) /* LSW of tceaddr */
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#define IOCC_CRESET (IOCC_BASE + 0xA0) /* comp reset reg */
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#define IOCC_BUS_MAP (IOCC_BASE + 0xA8) /* bus mapping reg */
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#define IOCC_IEE (IOCC_BASE + 0x180) /* intr enable */
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#define IOCC_IRR (IOCC_BASE + 0x188) /* intr request reg */
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#define IOCC_MIR (IOCC_BASE + 0x190) /* misc intr reg */
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#define IOCC_CPU_AVAIL(proc) \
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(IOCC_BASE + 0x1C0 + (proc * 4)) /* available procs */
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#define IOCC_XIVR(intr) \
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(IOCC_BASE + 0x200 + (intr * 4)) /* extr intr vector */
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#define IOCC_DMA_SLAVE_CTRL(slave) \
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(IOCC_BASE + 0x380 + (slave * 4)) /* slave control regs */
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#define IOCC_CHAN_STAT(chan) \
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(IOCC_BASE + 0x400 + (chan * 4)) /* channel stat regs */
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#define IOCC_EOI(intr) \
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(IOCC_BASE + 0x480 + (intr * 4)) /* ext intr vec */
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#define IOCC_ARBLEVEL(chan) \
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(IOCC_BASE + 0x500 + (chan * 4)) /* chan arb level en/disable */
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#define MAX_IOCC 2
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#endif /* _RS6000_IOCC_H_ */
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