617 lines
18 KiB
C
617 lines
18 KiB
C
/* $NetBSD: pdcsata.c,v 1.7 2006/06/20 02:39:58 christos Exp $ */
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/*
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* Copyright (c) 2004, Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Manuel Bouyer.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/types.h>
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#include <sys/malloc.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pciidereg.h>
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#include <dev/pci/pciidevar.h>
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#include <dev/ata/atareg.h>
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#include <dev/ata/satavar.h>
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#include <dev/ata/satareg.h>
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#define PDC203xx_NCHANNELS 4
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#define PDC40718_NCHANNELS 4
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#define PDC20575_NCHANNELS 3
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#define PDC203xx_BAR_IDEREGS 0x1c /* BAR where the IDE registers are mapped */
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#define PDC_CHANNELBASE(ch) 0x200 + ((ch) * 0x80)
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#define PDC_ERRMASK 0x00780700
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static void pdcsata_chip_map(struct pciide_softc *, struct pci_attach_args *);
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static void pdc203xx_setup_channel(struct ata_channel *);
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static void pdc203xx_irqack(struct ata_channel *);
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static int pdc203xx_dma_init(void *, int, int, void *, size_t, int);
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static void pdc203xx_dma_start(void *,int ,int);
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static int pdc203xx_dma_finish(void *, int, int, int);
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static int pdcsata_pci_intr(void *);
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static void pdcsata_do_reset(struct ata_channel *, int);
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/* PDC205xx, PDC405xx and PDC407xx. but tested only pdc40718 */
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static void pdc205xx_drv_probe(struct ata_channel *);
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static int pdcsata_match(struct device *, struct cfdata *, void *);
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static void pdcsata_attach(struct device *, struct device *, void *);
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CFATTACH_DECL(pdcsata, sizeof(struct pciide_softc),
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pdcsata_match, pdcsata_attach, NULL, NULL);
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static const struct pciide_product_desc pciide_pdcsata_products[] = {
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{ PCI_PRODUCT_PROMISE_PDC20318,
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0,
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"Promise PDC20318 SATA150 controller",
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pdcsata_chip_map,
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},
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{ PCI_PRODUCT_PROMISE_PDC20319,
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0,
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"Promise PDC20319 SATA150 controller",
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pdcsata_chip_map,
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},
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{ PCI_PRODUCT_PROMISE_PDC20371,
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0,
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"Promise PDC20371 SATA150 controller",
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pdcsata_chip_map,
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},
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{ PCI_PRODUCT_PROMISE_PDC20375,
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0,
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"Promise PDC20375 SATA150 controller",
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pdcsata_chip_map,
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},
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{ PCI_PRODUCT_PROMISE_PDC20376,
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0,
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"Promise PDC20376 SATA150 controller",
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pdcsata_chip_map,
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},
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{ PCI_PRODUCT_PROMISE_PDC20377,
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0,
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"Promise PDC20377 SATA150 controller",
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pdcsata_chip_map,
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},
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{ PCI_PRODUCT_PROMISE_PDC20378,
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0,
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"Promise PDC20378 SATA150 controller",
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pdcsata_chip_map,
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},
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{ PCI_PRODUCT_PROMISE_PDC20379,
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0,
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"Promise PDC20379 SATA150 controller",
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pdcsata_chip_map,
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},
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{ PCI_PRODUCT_PROMISE_PDC40718,
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0,
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"Promise PDC40718 SATA300 controller",
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pdcsata_chip_map,
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},
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{ PCI_PRODUCT_PROMISE_PDC40719,
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0,
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"Promise PDC40719 SATA300 controller",
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pdcsata_chip_map,
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},
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{ PCI_PRODUCT_PROMISE_PDC20571,
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0,
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"Promise PDC20571 SATA150 controller",
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pdcsata_chip_map,
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},
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{ PCI_PRODUCT_PROMISE_PDC20575,
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0,
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"Promise PDC20575 SATA150 controller",
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pdcsata_chip_map,
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},
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{ PCI_PRODUCT_PROMISE_PDC20579,
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0,
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"Promise PDC20579 SATA150 controller",
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pdcsata_chip_map,
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},
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{ 0,
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0,
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NULL,
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NULL
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}
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};
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static int
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pdcsata_match(struct device *parent, struct cfdata *match, void *aux)
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{
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struct pci_attach_args *pa = aux;
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) {
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if (pciide_lookup_product(pa->pa_id, pciide_pdcsata_products))
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return (2);
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}
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return (0);
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}
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static void
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pdcsata_attach(struct device *parent, struct device *self, void *aux)
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{
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struct pci_attach_args *pa = aux;
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struct pciide_softc *sc = (struct pciide_softc *)self;
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pciide_common_attach(sc, pa,
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pciide_lookup_product(pa->pa_id, pciide_pdcsata_products));
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}
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static void
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pdcsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
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{
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struct pciide_channel *cp;
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struct ata_channel *wdc_cp;
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struct wdc_regs *wdr;
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int channel, i;
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bus_size_t dmasize;
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pci_intr_handle_t intrhandle;
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const char *intrstr;
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/*
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* Promise SATA controllers have 3 or 4 channels,
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* the usual IDE registers are mapped in I/O space, with offsets.
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*/
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if (pci_intr_map(pa, &intrhandle) != 0) {
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aprint_error("%s: couldn't map interrupt\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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return;
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}
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intrstr = pci_intr_string(pa->pa_pc, intrhandle);
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sc->sc_pci_ih = pci_intr_establish(pa->pa_pc,
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intrhandle, IPL_BIO, pdcsata_pci_intr, sc);
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if (sc->sc_pci_ih == NULL) {
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aprint_error("%s: couldn't establish native-PCI interrupt",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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if (intrstr != NULL)
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aprint_normal(" at %s", intrstr);
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aprint_normal("\n");
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return;
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}
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aprint_normal("%s: interrupting at %s\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
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intrstr ? intrstr : "unknown interrupt");
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sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA,
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PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_dma_iot,
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&sc->sc_dma_ioh, NULL, &dmasize) == 0);
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if (!sc->sc_dma_ok) {
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aprint_error("%s: couldn't map bus-master DMA registers\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih);
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return;
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}
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sc->sc_dmat = pa->pa_dmat;
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if (pci_mapreg_map(pa, PDC203xx_BAR_IDEREGS,
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PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_ba5_st,
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&sc->sc_ba5_sh, NULL, NULL) != 0) {
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aprint_error("%s: couldn't map IDE registers\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, dmasize);
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pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih);
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return;
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}
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aprint_normal("%s: bus-master DMA support present\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16;
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if (sc->sc_dma_ok) {
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
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}
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if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
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PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
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sc->sc_wdcdev.irqack = pdc203xx_irqack;
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sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
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sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
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sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
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sc->sc_wdcdev.sc_atac.atac_set_modes = pdc203xx_setup_channel;
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sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
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sc->sc_wdcdev.reset = pdcsata_do_reset;
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switch (sc->sc_pp->ide_product) {
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case PCI_PRODUCT_PROMISE_PDC20318:
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case PCI_PRODUCT_PROMISE_PDC20319:
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case PCI_PRODUCT_PROMISE_PDC20371:
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case PCI_PRODUCT_PROMISE_PDC20375:
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case PCI_PRODUCT_PROMISE_PDC20376:
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case PCI_PRODUCT_PROMISE_PDC20377:
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case PCI_PRODUCT_PROMISE_PDC20378:
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case PCI_PRODUCT_PROMISE_PDC20379:
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default:
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bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, 0x00ff0033);
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sc->sc_wdcdev.sc_atac.atac_nchannels =
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(bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x48) & 0x02) ?
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PDC203xx_NCHANNELS : 3;
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break;
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case PCI_PRODUCT_PROMISE_PDC40718:
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case PCI_PRODUCT_PROMISE_PDC40719:
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case PCI_PRODUCT_PROMISE_PDC20571:
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bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 0x00ff00ff);
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sc->sc_wdcdev.sc_atac.atac_nchannels = PDC40718_NCHANNELS;
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sc->sc_wdcdev.sc_atac.atac_probe = pdc205xx_drv_probe;
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break;
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case PCI_PRODUCT_PROMISE_PDC20575:
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case PCI_PRODUCT_PROMISE_PDC20579:
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bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 0x00ff00ff);
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sc->sc_wdcdev.sc_atac.atac_nchannels = PDC20575_NCHANNELS;
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sc->sc_wdcdev.sc_atac.atac_probe = pdc205xx_drv_probe;
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break;
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}
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wdc_allocate_regs(&sc->sc_wdcdev);
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sc->sc_wdcdev.dma_arg = sc;
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sc->sc_wdcdev.dma_init = pdc203xx_dma_init;
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sc->sc_wdcdev.dma_start = pdc203xx_dma_start;
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sc->sc_wdcdev.dma_finish = pdc203xx_dma_finish;
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for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
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channel++) {
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cp = &sc->pciide_channels[channel];
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sc->wdc_chanarray[channel] = &cp->ata_channel;
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cp->ih = sc->sc_pci_ih;
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cp->name = NULL;
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cp->ata_channel.ch_channel = channel;
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cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
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cp->ata_channel.ch_queue =
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malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT);
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cp->ata_channel.ch_ndrive = 2;
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if (cp->ata_channel.ch_queue == NULL) {
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aprint_error("%s channel %d: "
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"can't allocate memory for command queue\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel);
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goto next_channel;
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}
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wdc_cp = &cp->ata_channel;
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wdr = CHAN_TO_WDC_REGS(wdc_cp);
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wdr->ctl_iot = sc->sc_ba5_st;
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wdr->cmd_iot = sc->sc_ba5_st;
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if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
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0x0238 + (channel << 7), 1, &wdr->ctl_ioh) != 0) {
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aprint_error("%s: couldn't map channel %d ctl regs\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
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channel);
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goto next_channel;
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}
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for (i = 0; i < WDC_NREG; i++) {
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if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
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0x0200 + (i << 2) + (channel << 7), i == 0 ? 4 : 1,
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&wdr->cmd_iohs[i]) != 0) {
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aprint_error("%s: couldn't map channel %d cmd "
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"regs\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
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channel);
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goto next_channel;
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}
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}
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wdc_init_shadow_regs(wdc_cp);
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/*
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* subregion de busmaster registers. They're spread all over
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* the controller's register space :(. They are also 4 bytes
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* sized, with some specific extentions in the extra bits.
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* It also seems that the IDEDMA_CTL register isn't available.
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*/
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if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
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0x260 + (channel << 7), 1,
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&cp->dma_iohs[IDEDMA_CMD]) != 0) {
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aprint_normal("%s channel %d: can't subregion DMA "
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"registers\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel);
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goto next_channel;
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}
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if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
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0x244 + (channel << 7), 4,
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&cp->dma_iohs[IDEDMA_TBL]) != 0) {
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aprint_normal("%s channel %d: can't subregion DMA "
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"registers\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel);
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goto next_channel;
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}
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wdcattach(wdc_cp);
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bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0,
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(bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD],
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0) & ~0x00003f9f) | (channel + 1));
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bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh,
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(channel + 1) << 2, 0x00000001);
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next_channel:
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continue;
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}
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return;
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}
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static void
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pdc203xx_setup_channel(struct ata_channel *chp)
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{
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struct ata_drive_datas *drvp;
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int drive, s;
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struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
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pciide_channel_dma_setup(cp);
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for (drive = 0; drive < 2; drive++) {
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drvp = &chp->ch_drive[drive];
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if ((drvp->drive_flags & DRIVE) == 0)
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continue;
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if (drvp->drive_flags & DRIVE_UDMA) {
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s = splbio();
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drvp->drive_flags &= ~DRIVE_DMA;
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splx(s);
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}
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}
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}
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static int
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pdcsata_pci_intr(void *arg)
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{
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struct pciide_softc *sc = arg;
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struct pciide_channel *cp;
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struct ata_channel *wdc_cp;
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int i, rv, crv;
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u_int32_t scr, status, chanbase;
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rv = 0;
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scr = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40);
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if (scr == 0xffffffff) return(rv);
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bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40, scr & 0x0000ffff);
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scr = scr & 0x0000ffff;
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if (!scr) return(rv);
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for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
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cp = &sc->pciide_channels[i];
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wdc_cp = &cp->ata_channel;
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if (scr & (1 << (i + 1))) {
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chanbase = PDC_CHANNELBASE(i) + 0x48;
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status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase);
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if (status & PDC_ERRMASK) {
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chanbase = PDC_CHANNELBASE(i) + 0x60;
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status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase);
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status |= 0x800;
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bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status);
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status &= ~0x800;
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bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status);
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status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase);
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continue;
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}
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crv = wdcintr(wdc_cp);
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if (crv == 0) {
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printf("%s:%d: bogus intr (reg 0x%x)\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
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i, scr);
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} else
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rv = 1;
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}
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}
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return rv;
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}
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static void
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pdc203xx_irqack(struct ata_channel *chp)
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{
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struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
|
|
struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
|
|
|
|
bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0,
|
|
(bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD],
|
|
0) & ~0x00003f9f) | (cp->ata_channel.ch_channel + 1));
|
|
bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh,
|
|
(cp->ata_channel.ch_channel + 1) << 2, 0x00000001);
|
|
}
|
|
|
|
static int
|
|
pdc203xx_dma_init(void *v, int channel, int drive, void *databuf,
|
|
size_t datalen, int flags)
|
|
{
|
|
struct pciide_softc *sc = v;
|
|
|
|
return pciide_dma_dmamap_setup(sc, channel, drive,
|
|
databuf, datalen, flags);
|
|
}
|
|
|
|
static void
|
|
pdc203xx_dma_start(void *v, int channel, int drive)
|
|
{
|
|
struct pciide_softc *sc = v;
|
|
struct pciide_channel *cp = &sc->pciide_channels[channel];
|
|
struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive];
|
|
|
|
/* Write table addr */
|
|
bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0,
|
|
dma_maps->dmamap_table->dm_segs[0].ds_addr);
|
|
/* start DMA engine */
|
|
bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0,
|
|
(bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD],
|
|
0) & ~0xc0) | ((dma_maps->dma_flags & WDC_DMA_READ) ? 0x80 : 0xc0));
|
|
}
|
|
|
|
static int
|
|
pdc203xx_dma_finish(void *v, int channel, int drive, int force)
|
|
{
|
|
struct pciide_softc *sc = v;
|
|
struct pciide_channel *cp = &sc->pciide_channels[channel];
|
|
struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive];
|
|
|
|
/* stop DMA channel */
|
|
bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0,
|
|
(bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD],
|
|
0) & ~0x80));
|
|
|
|
/* Unload the map of the data buffer */
|
|
bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0,
|
|
dma_maps->dmamap_xfer->dm_mapsize,
|
|
(dma_maps->dma_flags & WDC_DMA_READ) ?
|
|
BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
|
|
bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#define PDC205_REGADDR(base,ch) ((base)+((ch)<<8))
|
|
#define PDC205_SSTATUS(ch) PDC205_REGADDR(0x400,ch)
|
|
#define PDC205_SERROR(ch) PDC205_REGADDR(0x404,ch)
|
|
#define PDC205_SCONTROL(ch) PDC205_REGADDR(0x408,ch)
|
|
#define PDC205_MULTIPLIER(ch) PDC205_REGADDR(0x4e8,ch)
|
|
|
|
|
|
#define SCONTROL_WRITE(sc,channel,scontrol) \
|
|
bus_space_write_4((sc)->sc_ba5_st, (sc)->sc_ba5_sh, \
|
|
PDC205_SCONTROL(channel), scontrol)
|
|
|
|
#define SSTATUS_READ(sc,channel) \
|
|
bus_space_read_4((sc)->sc_ba5_st, (sc)->sc_ba5_sh, \
|
|
PDC205_SSTATUS(channel))
|
|
|
|
|
|
|
|
static void
|
|
pdcsata_do_reset(struct ata_channel *chp, int poll)
|
|
{
|
|
struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
|
|
int reset, status, i, chanbase;
|
|
|
|
/* reset SATA */
|
|
reset = (1 << 11);
|
|
chanbase = PDC_CHANNELBASE(chp->ch_channel) + 0x60;
|
|
for (i = 0; i < 11;i ++) {
|
|
status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase);
|
|
if (status & reset) break;
|
|
delay(100);
|
|
status |= reset;
|
|
bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status);
|
|
}
|
|
status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase);
|
|
status &= ~reset;
|
|
bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status);
|
|
status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase);
|
|
|
|
wdc_do_reset(chp, poll);
|
|
|
|
}
|
|
|
|
static void
|
|
pdc205xx_drv_probe(struct ata_channel *chp)
|
|
{
|
|
struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
|
|
struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp);
|
|
u_int32_t scontrol, sstatus;
|
|
u_int16_t scnt, sn, cl, ch;
|
|
int i, s;
|
|
|
|
/* XXX This should be done by other code. */
|
|
for (i = 0; i < 2; i++) {
|
|
chp->ch_drive[i].chnl_softc = chp;
|
|
chp->ch_drive[i].drive = i;
|
|
}
|
|
|
|
SCONTROL_WRITE(sc, chp->ch_channel, 0);
|
|
delay(50*1000);
|
|
|
|
scontrol = SControl_DET_INIT | SControl_SPD_ANY | SControl_IPM_NONE;
|
|
SCONTROL_WRITE(sc,chp->ch_channel,scontrol);
|
|
delay(50*1000);
|
|
|
|
scontrol &= ~SControl_DET_INIT;
|
|
SCONTROL_WRITE(sc,chp->ch_channel,scontrol);
|
|
delay(50*1000);
|
|
|
|
sstatus = SSTATUS_READ(sc,chp->ch_channel);
|
|
|
|
switch (sstatus & SStatus_DET_mask) {
|
|
case SStatus_DET_NODEV:
|
|
/* No Device; be silent. */
|
|
break;
|
|
|
|
case SStatus_DET_DEV_NE:
|
|
aprint_error("%s: port %d: device connected, but "
|
|
"communication not established\n",
|
|
sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel);
|
|
break;
|
|
|
|
case SStatus_DET_OFFLINE:
|
|
aprint_error("%s: port %d: PHY offline\n",
|
|
sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel);
|
|
break;
|
|
|
|
case SStatus_DET_DEV:
|
|
bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0,
|
|
WDSD_IBM);
|
|
delay(10); /* 400ns delay */
|
|
scnt = bus_space_read_2(wdr->cmd_iot,
|
|
wdr->cmd_iohs[wd_seccnt], 0);
|
|
sn = bus_space_read_2(wdr->cmd_iot,
|
|
wdr->cmd_iohs[wd_sector], 0);
|
|
cl = bus_space_read_2(wdr->cmd_iot,
|
|
wdr->cmd_iohs[wd_cyl_lo], 0);
|
|
ch = bus_space_read_2(wdr->cmd_iot,
|
|
wdr->cmd_iohs[wd_cyl_hi], 0);
|
|
#if 0
|
|
printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n",
|
|
sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel,
|
|
scnt, sn, cl, ch);
|
|
#endif
|
|
/*
|
|
* scnt and sn are supposed to be 0x1 for ATAPI, but in some
|
|
* cases we get wrong values here, so ignore it.
|
|
*/
|
|
s = splbio();
|
|
if (cl == 0x14 && ch == 0xeb)
|
|
chp->ch_drive[0].drive_flags |= DRIVE_ATAPI;
|
|
else
|
|
chp->ch_drive[0].drive_flags |= DRIVE_ATA;
|
|
splx(s);
|
|
#if 0
|
|
aprint_normal("%s: port %d: device present, speed: %s\n",
|
|
sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel,
|
|
sata_speed(sstatus));
|
|
#endif
|
|
break;
|
|
|
|
default:
|
|
aprint_error("%s: port %d: unknown SStatus: 0x%08x\n",
|
|
sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel,
|
|
sstatus);
|
|
}
|
|
}
|