874 lines
22 KiB
C
874 lines
22 KiB
C
/* $NetBSD: fpudispatch.c,v 1.1 2002/06/05 01:04:25 fredette Exp $ */
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/*
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* (c) Copyright 1991 HEWLETT-PACKARD COMPANY
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*
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* To anyone who acknowledges that this file is provided "AS IS"
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* without any express or implied warranty:
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* permission to use, copy, modify, and distribute this file
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* for any purpose is hereby granted without fee, provided that
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* the above copyright notice and this notice appears in all
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* copies, and that the name of Hewlett-Packard Company not be
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* used in advertising or publicity pertaining to distribution
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* of the software without specific, written prior permission.
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* Hewlett-Packard Company makes no representations about the
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* suitability of this software for any purpose.
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*/
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/* Source: /n/schirf/u/baford/CVS/mach4-parisc/kernel/parisc/fpudispatch.c,v
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* Revision: 1.4 Author: mike
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* State: Exp Locker:
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* Date: 1994/07/21 17:36:35
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*/
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#include <sys/types.h>
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#include <sys/systm.h>
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#include "../spmath/float.h"
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/*
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* XXX fredette - hack to glue the bulk of
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* the spmath library to this dispatcher.
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*/
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#define dbl_integer unsigned
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#define sgl_floating_point unsigned
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#define dbl_floating_point unsigned
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#include "../spmath/sgl_float.h"
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#include "../spmath/dbl_float.h"
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#include "../spmath/cnv_float.h"
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#include "../spmath/md.h"
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#include "../spmath/fpudispatch.h"
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/*
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* version of EMULATION software for COPR,0,0 instruction
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*/
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#define EMULATION_VERSION 3
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#define COPR_INST 0x30000000
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/*
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* definition of extru macro. If pos and len are constants, the compiler
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* will generate an extru instruction when optimized
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*/
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#define extru(r,pos,len) (((r) >> (31-(pos))) & (( 1 << (len)) - 1))
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/* definitions of bit field locations in the instruction */
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#define fpmajorpos 5
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#define fpr1pos 10
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#define fpr2pos 15
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#define fptpos 31
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#define fpsubpos 18
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#define fpclass1subpos 16
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#define fpclasspos 22
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#define fpfmtpos 20
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#define fpdfpos 18
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/*
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* the following are the extra bits for the 0E major op
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*/
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#define fpxr1pos 24
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#define fpxr2pos 19
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#define fpxtpos 25
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#define fpxpos 23
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#define fp0efmtpos 20
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/*
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* the following are for the multi-ops
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*/
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#define fprm1pos 10
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#define fprm2pos 15
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#define fptmpos 31
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#define fprapos 25
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#define fptapos 20
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#define fpmultifmt 26
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/*
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* offset to constant zero in the FP emulation registers
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*/
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#define fpzeroreg (32*sizeof(double)/sizeof(unsigned))
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/*
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* extract the major opcode from the instruction
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*/
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#define get_major(op) extru(op,fpmajorpos,6)
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/*
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* extract the two bit class field from the FP instruction. The class is at bit
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* positions 21-22
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*/
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#define get_class(op) extru(op,fpclasspos,2)
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/*
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* extract the 3 bit subop field. For all but class 1 instructions, it is
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* located at bit positions 16-18
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*/
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#define get_subop(op) extru(op,fpsubpos,3)
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/*
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* extract the 2 bit subop field from class 1 instructions. It is located
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* at bit positions 15-16
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*/
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#define get_subop1(op) extru(op,fpclass1subpos,2)
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/* definitions of unimplemented exceptions */
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#define MAJOR_0C_EXCP UNIMPLEMENTEDEXCEPTION
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#define MAJOR_0E_EXCP UNIMPLEMENTEDEXCEPTION
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#define MAJOR_06_EXCP UNIMPLEMENTEDEXCEPTION
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#define MAJOR_26_EXCP UNIMPLEMENTEDEXCEPTION
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#define PA83_UNIMP_EXCP UNIMPLEMENTEDEXCEPTION
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int
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decode_0c(ir,class,subop,fpregs)
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unsigned ir,class,subop;
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unsigned fpregs[];
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{
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unsigned r1,r2,t; /* operand register offsets */
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unsigned fmt; /* also sf for class 1 conversions */
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unsigned df; /* for class 1 conversions */
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unsigned *status;
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if (ir == COPR_INST) {
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fpregs[0] = EMULATION_VERSION << 11;
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return(NOEXCEPTION);
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}
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status = &fpregs[0]; /* fp status register */
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r1 = extru(ir,fpr1pos,5) * sizeof(double)/sizeof(unsigned);
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if (r1 == 0) /* map fr0 source to constant zero */
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r1 = fpzeroreg;
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t = extru(ir,fptpos,5) * sizeof(double)/sizeof(unsigned);
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if (t == 0 && class != 2) /* don't allow fr0 as a dest */
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return(MAJOR_0C_EXCP);
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fmt = extru(ir,fpfmtpos,2); /* get fmt completer */
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switch (class) {
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case 0:
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switch (subop) {
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case 0: /* COPR 0,0 emulated above*/
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case 1:
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case 6:
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case 7:
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return(MAJOR_0C_EXCP);
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case 2: /* FCPY */
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switch (fmt) {
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case 2: /* illegal */
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return(MAJOR_0C_EXCP);
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case 3: /* quad */
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fpregs[t+3] = fpregs[r1+3];
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fpregs[t+2] = fpregs[r1+2];
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case 1: /* double */
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fpregs[t+1] = fpregs[r1+1];
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case 0: /* single */
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fpregs[t] = fpregs[r1];
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return(NOEXCEPTION);
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}
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case 3: /* FABS */
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switch (fmt) {
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case 2: /* illegal */
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return(MAJOR_0C_EXCP);
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case 3: /* quad */
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fpregs[t+3] = fpregs[r1+3];
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fpregs[t+2] = fpregs[r1+2];
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case 1: /* double */
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fpregs[t+1] = fpregs[r1+1];
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case 0: /* single */
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/* copy and clear sign bit */
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fpregs[t] = fpregs[r1] & 0x7fffffff;
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return(NOEXCEPTION);
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}
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case 4: /* FSQRT */
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switch (fmt) {
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case 0:
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return(sgl_fsqrt(&fpregs[r1],
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&fpregs[t],status));
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case 1:
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return(dbl_fsqrt(&fpregs[r1],
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&fpregs[t],status));
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case 2:
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case 3: /* quad not implemented */
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return(MAJOR_0C_EXCP);
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}
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case 5: /* FRND */
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switch (fmt) {
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case 0:
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return(sgl_frnd(&fpregs[r1],
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&fpregs[t],status));
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case 1:
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return(dbl_frnd(&fpregs[r1],
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&fpregs[t],status));
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case 2:
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case 3: /* quad not implemented */
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return(MAJOR_0C_EXCP);
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}
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} /* end of switch (subop) */
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case 1: /* class 1 */
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df = extru(ir,fpdfpos,2); /* get dest format */
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if ((df & 2) || (fmt & 2)) {
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/*
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* fmt's 2 and 3 are illegal of not implemented
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* quad conversions
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*/
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return(MAJOR_0C_EXCP);
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}
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/*
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* encode source and dest formats into 2 bits.
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* high bit is source, low bit is dest.
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* bit = 1 --> double precision
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*/
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fmt = (fmt << 1) | df;
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switch (subop) {
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case 0: /* FCNVFF */
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switch(fmt) {
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case 0: /* sgl/sgl */
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return(MAJOR_0C_EXCP);
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case 1: /* sgl/dbl */
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return(sgl_to_dbl_fcnvff(&fpregs[r1],
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&fpregs[t],status));
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case 2: /* dbl/sgl */
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return(dbl_to_sgl_fcnvff(&fpregs[r1],
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&fpregs[t],status));
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case 3: /* dbl/dbl */
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return(MAJOR_0C_EXCP);
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}
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case 1: /* FCNVXF */
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switch(fmt) {
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case 0: /* sgl/sgl */
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return(sgl_to_sgl_fcnvxf(&fpregs[r1],
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&fpregs[t],status));
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case 1: /* sgl/dbl */
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return(sgl_to_dbl_fcnvxf(&fpregs[r1],
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&fpregs[t],status));
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case 2: /* dbl/sgl */
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return(dbl_to_sgl_fcnvxf(&fpregs[r1],
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&fpregs[t],status));
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case 3: /* dbl/dbl */
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return(dbl_to_dbl_fcnvxf(&fpregs[r1],
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&fpregs[t],status));
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}
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case 2: /* FCNVFX */
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switch(fmt) {
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case 0: /* sgl/sgl */
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return(sgl_to_sgl_fcnvfx(&fpregs[r1],
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&fpregs[t],status));
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case 1: /* sgl/dbl */
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return(sgl_to_dbl_fcnvfx(&fpregs[r1],
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&fpregs[t],status));
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case 2: /* dbl/sgl */
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return(dbl_to_sgl_fcnvfx(&fpregs[r1],
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&fpregs[t],status));
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case 3: /* dbl/dbl */
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return(dbl_to_dbl_fcnvfx(&fpregs[r1],
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&fpregs[t],status));
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}
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case 3: /* FCNVFXT */
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switch(fmt) {
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case 0: /* sgl/sgl */
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return(sgl_to_sgl_fcnvfxt(&fpregs[r1],
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&fpregs[t],status));
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case 1: /* sgl/dbl */
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return(sgl_to_dbl_fcnvfxt(&fpregs[r1],
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&fpregs[t],status));
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case 2: /* dbl/sgl */
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return(dbl_to_sgl_fcnvfxt(&fpregs[r1],
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&fpregs[t],status));
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case 3: /* dbl/dbl */
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return(dbl_to_dbl_fcnvfxt(&fpregs[r1],
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&fpregs[t],status));
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}
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} /* end of switch subop */
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case 2: /* class 2 */
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r2 = extru(ir, fpr2pos, 5) * sizeof(double)/sizeof(unsigned);
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if (r2 == 0)
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r2 = fpzeroreg;
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switch (subop) {
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case 2:
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case 3:
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case 4:
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case 5:
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case 6:
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case 7:
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return(MAJOR_0C_EXCP);
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case 0: /* FCMP */
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switch (fmt) {
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case 0:
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return(sgl_fcmp(&fpregs[r1],&fpregs[r2],
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extru(ir,fptpos,5),status));
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case 1:
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return(dbl_fcmp(&fpregs[r1],&fpregs[r2],
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extru(ir,fptpos,5),status));
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case 2: /* illegal */
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case 3: /* quad not implemented */
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return(MAJOR_0C_EXCP);
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}
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case 1: /* FTEST */
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switch (fmt) {
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case 0:
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/*
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* arg0 is not used
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* second param is the t field used for
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* ftest,acc and ftest,rej
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*/
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/* XXX fredette - broken */
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#if 0
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return(ftest(0,extru(ir,fptpos,5),
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&fpregs[0]));
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#else
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panic("ftest");
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#endif
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case 1:
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case 2:
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case 3:
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return(MAJOR_0C_EXCP);
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}
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} /* end if switch for class 2*/
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case 3: /* class 3 */
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r2 = extru(ir,fpr2pos,5) * sizeof(double)/sizeof(unsigned);
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if (r2 == 0)
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r2 = fpzeroreg;
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switch (subop) {
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case 5:
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case 6:
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case 7:
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return(MAJOR_0C_EXCP);
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case 0: /* FADD */
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switch (fmt) {
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case 0:
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return(sgl_fadd(&fpregs[r1],&fpregs[r2],
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&fpregs[t],status));
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case 1:
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return(dbl_fadd(&fpregs[r1],&fpregs[r2],
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&fpregs[t],status));
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case 2: /* illegal */
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case 3: /* quad not implemented */
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return(MAJOR_0C_EXCP);
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}
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case 1: /* FSUB */
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switch (fmt) {
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case 0:
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return(sgl_fsub(&fpregs[r1],&fpregs[r2],
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&fpregs[t],status));
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case 1:
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return(dbl_fsub(&fpregs[r1],&fpregs[r2],
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&fpregs[t],status));
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case 2: /* illegal */
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case 3: /* quad not implemented */
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return(MAJOR_0C_EXCP);
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}
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case 2: /* FMPY */
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switch (fmt) {
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case 0:
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return(sgl_fmpy(&fpregs[r1],&fpregs[r2],
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&fpregs[t],status));
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case 1:
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return(dbl_fmpy(&fpregs[r1],&fpregs[r2],
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&fpregs[t],status));
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case 2: /* illegal */
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case 3: /* quad not implemented */
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return(MAJOR_0C_EXCP);
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}
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case 3: /* FDIV */
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switch (fmt) {
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case 0:
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return(sgl_fdiv(&fpregs[r1],&fpregs[r2],
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&fpregs[t],status));
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case 1:
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return(dbl_fdiv(&fpregs[r1],&fpregs[r2],
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&fpregs[t],status));
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case 2: /* illegal */
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case 3: /* quad not implemented */
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return(MAJOR_0C_EXCP);
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}
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case 4: /* FREM */
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switch (fmt) {
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case 0:
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return(sgl_frem(&fpregs[r1],&fpregs[r2],
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&fpregs[t],status));
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case 1:
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return(dbl_frem(&fpregs[r1],&fpregs[r2],
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&fpregs[t],status));
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case 2: /* illegal */
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case 3: /* quad not implemented */
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return(MAJOR_0C_EXCP);
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}
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} /* end of class 3 switch */
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} /* end of switch(class) */
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panic("decode_0c");
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}
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int
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decode_0e(ir,class,subop,fpregs)
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unsigned ir,class,subop;
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unsigned fpregs[];
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{
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unsigned r1,r2,t; /* operand register offsets */
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unsigned fmt; /* also sf for class 1 conversions */
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unsigned df; /* dest format for class 1 conversions */
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unsigned *status;
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status = &fpregs[0];
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r1 = ((extru(ir,fpr1pos,5)<<1)|(extru(ir,fpxr1pos,1)));
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if (r1 == 0)
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r1 = fpzeroreg;
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t = ((extru(ir,fptpos,5)<<1)|(extru(ir,fpxtpos,1)));
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if (t == 0 && class != 2)
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return(MAJOR_0E_EXCP);
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if (class < 2) /* class 0 or 1 has 2 bit fmt */
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fmt = extru(ir,fpfmtpos,2);
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else /* class 2 and 3 have 1 bit fmt */
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fmt = extru(ir,fp0efmtpos,1);
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switch (class) {
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case 0:
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switch (subop) {
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case 0: /* unimplemented */
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case 1:
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case 6:
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case 7:
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return(MAJOR_0E_EXCP);
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case 2: /* FCPY */
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switch (fmt) {
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case 2:
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case 3:
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return(MAJOR_0E_EXCP);
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case 1: /* double */
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fpregs[t+1] = fpregs[r1+1];
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case 0: /* single */
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fpregs[t] = fpregs[r1];
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return(NOEXCEPTION);
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}
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case 3: /* FABS */
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switch (fmt) {
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case 2:
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case 3:
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return(MAJOR_0E_EXCP);
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case 1: /* double */
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fpregs[t+1] = fpregs[r1+1];
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case 0: /* single */
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fpregs[t] = fpregs[r1] & 0x7fffffff;
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return(NOEXCEPTION);
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}
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case 4: /* FSQRT */
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switch (fmt) {
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case 0:
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return(sgl_fsqrt(&fpregs[r1],
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&fpregs[t], status));
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case 1:
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return(dbl_fsqrt(&fpregs[r1],
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&fpregs[t], status));
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case 2:
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case 3:
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return(MAJOR_0E_EXCP);
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}
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case 5: /* FRMD */
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switch (fmt) {
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case 0:
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return(sgl_frnd(&fpregs[r1],
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&fpregs[t], status));
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case 1:
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return(dbl_frnd(&fpregs[r1],
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&fpregs[t], status));
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case 2:
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case 3:
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return(MAJOR_0E_EXCP);
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}
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} /* end of switch (subop */
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case 1: /* class 1 */
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df = extru(ir,fpdfpos,2); /* get dest format */
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if ((df & 2) || (fmt & 2))
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return(MAJOR_0E_EXCP);
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fmt = (fmt << 1) | df;
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switch (subop) {
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case 0: /* FCNVFF */
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switch(fmt) {
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case 0: /* sgl/sgl */
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return(MAJOR_0E_EXCP);
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case 1: /* sgl/dbl */
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return(sgl_to_dbl_fcnvff(&fpregs[r1],
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&fpregs[t],status));
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case 2: /* dbl/sgl */
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return(dbl_to_sgl_fcnvff(&fpregs[r1],
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&fpregs[t],status));
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case 3: /* dbl/dbl */
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return(MAJOR_0E_EXCP);
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}
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case 1: /* FCNVXF */
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switch(fmt) {
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case 0: /* sgl/sgl */
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return(sgl_to_sgl_fcnvxf(&fpregs[r1],
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&fpregs[t],status));
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case 1: /* sgl/dbl */
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return(sgl_to_dbl_fcnvxf(&fpregs[r1],
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&fpregs[t],status));
|
|
case 2: /* dbl/sgl */
|
|
return(dbl_to_sgl_fcnvxf(&fpregs[r1],
|
|
&fpregs[t],status));
|
|
case 3: /* dbl/dbl */
|
|
return(dbl_to_dbl_fcnvxf(&fpregs[r1],
|
|
&fpregs[t],status));
|
|
}
|
|
case 2: /* FCNVFX */
|
|
switch(fmt) {
|
|
case 0: /* sgl/sgl */
|
|
return(sgl_to_sgl_fcnvfx(&fpregs[r1],
|
|
&fpregs[t],status));
|
|
case 1: /* sgl/dbl */
|
|
return(sgl_to_dbl_fcnvfx(&fpregs[r1],
|
|
&fpregs[t],status));
|
|
case 2: /* dbl/sgl */
|
|
return(dbl_to_sgl_fcnvfx(&fpregs[r1],
|
|
&fpregs[t],status));
|
|
case 3: /* dbl/dbl */
|
|
return(dbl_to_dbl_fcnvfx(&fpregs[r1],
|
|
&fpregs[t],status));
|
|
}
|
|
case 3: /* FCNVFXT */
|
|
switch(fmt) {
|
|
case 0: /* sgl/sgl */
|
|
return(sgl_to_sgl_fcnvfxt(&fpregs[r1],
|
|
&fpregs[t],status));
|
|
case 1: /* sgl/dbl */
|
|
return(sgl_to_dbl_fcnvfxt(&fpregs[r1],
|
|
&fpregs[t],status));
|
|
case 2: /* dbl/sgl */
|
|
return(dbl_to_sgl_fcnvfxt(&fpregs[r1],
|
|
&fpregs[t],status));
|
|
case 3: /* dbl/dbl */
|
|
return(dbl_to_dbl_fcnvfxt(&fpregs[r1],
|
|
&fpregs[t],status));
|
|
}
|
|
} /* end of switch subop */
|
|
case 2: /* class 2 */
|
|
r2 = ((extru(ir,fpr2pos,5)<<1)|(extru(ir,fpxr2pos,1)));
|
|
if (r2 == 0)
|
|
r2 = fpzeroreg;
|
|
switch (subop) {
|
|
case 1:
|
|
case 2:
|
|
case 3:
|
|
case 4:
|
|
case 5:
|
|
case 6:
|
|
case 7:
|
|
return(MAJOR_0E_EXCP);
|
|
case 0: /* FCMP */
|
|
switch (fmt) {
|
|
/*
|
|
* fmt is only 1 bit long
|
|
*/
|
|
case 0:
|
|
return(sgl_fcmp(&fpregs[r1],&fpregs[r2],
|
|
extru(ir,fptpos,5),status));
|
|
case 1:
|
|
return(dbl_fcmp(&fpregs[r1],&fpregs[r2],
|
|
extru(ir,fptpos,5),status));
|
|
}
|
|
} /* end of switch for class 2 */
|
|
case 3: /* class 3 */
|
|
r2 = ((extru(ir,fpr2pos,5)<<1)|(extru(ir,fpxr2pos,1)));
|
|
if (r2 == 0)
|
|
r2 = fpzeroreg;
|
|
switch (subop) {
|
|
case 5:
|
|
case 6:
|
|
case 7:
|
|
return(MAJOR_0E_EXCP);
|
|
|
|
/*
|
|
* Note that fmt is only 1 bit for class 3 */
|
|
case 0: /* FADD */
|
|
switch (fmt) {
|
|
case 0:
|
|
return(sgl_fadd(&fpregs[r1],&fpregs[r2],
|
|
&fpregs[t],status));
|
|
case 1:
|
|
return(dbl_fadd(&fpregs[r1],&fpregs[r2],
|
|
&fpregs[t],status));
|
|
}
|
|
case 1: /* FSUB */
|
|
switch (fmt) {
|
|
case 0:
|
|
return(sgl_fsub(&fpregs[r1],&fpregs[r2],
|
|
&fpregs[t],status));
|
|
case 1:
|
|
return(dbl_fsub(&fpregs[r1],&fpregs[r2],
|
|
&fpregs[t],status));
|
|
}
|
|
case 2: /* FMPY or XMPYU */
|
|
/*
|
|
* check for integer multiply (x bit set)
|
|
*/
|
|
if (extru(ir,fpxpos,1)) {
|
|
/*
|
|
* emulate XMPYU
|
|
*/
|
|
switch (fmt) {
|
|
case 0:
|
|
/*
|
|
* bad instruction if t specifies
|
|
* the right half of a register
|
|
*/
|
|
if (t & 1)
|
|
return(MAJOR_0E_EXCP);
|
|
/* XXX fredette - broken. */
|
|
#if 0
|
|
impyu(&fpregs[r1],&fpregs[r2],
|
|
&fpregs[t]);
|
|
return(NOEXCEPTION);
|
|
#else
|
|
panic("impyu");
|
|
#endif
|
|
case 1:
|
|
return(MAJOR_0E_EXCP);
|
|
}
|
|
}
|
|
else { /* FMPY */
|
|
switch (fmt) {
|
|
case 0:
|
|
return(sgl_fmpy(&fpregs[r1],
|
|
&fpregs[r2],&fpregs[t],status));
|
|
case 1:
|
|
return(dbl_fmpy(&fpregs[r1],
|
|
&fpregs[r2],&fpregs[t],status));
|
|
}
|
|
}
|
|
case 3: /* FDIV */
|
|
switch (fmt) {
|
|
case 0:
|
|
return(sgl_fdiv(&fpregs[r1],&fpregs[r2],
|
|
&fpregs[t],status));
|
|
case 1:
|
|
return(dbl_fdiv(&fpregs[r1],&fpregs[r2],
|
|
&fpregs[t],status));
|
|
}
|
|
case 4: /* FREM */
|
|
switch (fmt) {
|
|
case 0:
|
|
return(sgl_frem(&fpregs[r1],&fpregs[r2],
|
|
&fpregs[t],status));
|
|
case 1:
|
|
return(dbl_frem(&fpregs[r1],&fpregs[r2],
|
|
&fpregs[t],status));
|
|
}
|
|
} /* end of class 3 switch */
|
|
} /* end of switch(class) */
|
|
panic("decode_0e");
|
|
}
|
|
|
|
|
|
/*
|
|
* routine to decode the 06 (FMPYADD and FMPYCFXT) instruction
|
|
*/
|
|
int
|
|
decode_06(ir,fpregs)
|
|
unsigned ir;
|
|
unsigned fpregs[];
|
|
{
|
|
unsigned rm1, rm2, tm, ra, ta; /* operands */
|
|
unsigned fmt;
|
|
unsigned error = 0;
|
|
unsigned status;
|
|
union {
|
|
double dbl;
|
|
float flt;
|
|
struct { unsigned i1; unsigned i2; } ints;
|
|
} mtmp, atmp;
|
|
|
|
|
|
status = fpregs[0]; /* use a local copy of status reg */
|
|
fmt = extru(ir, fpmultifmt, 1); /* get sgl/dbl flag */
|
|
if (fmt == 0) { /* DBL */
|
|
rm1 = extru(ir, fprm1pos, 5) * sizeof(double)/sizeof(unsigned);
|
|
if (rm1 == 0)
|
|
rm1 = fpzeroreg;
|
|
rm2 = extru(ir, fprm2pos, 5) * sizeof(double)/sizeof(unsigned);
|
|
if (rm2 == 0)
|
|
rm2 = fpzeroreg;
|
|
tm = extru(ir, fptmpos, 5) * sizeof(double)/sizeof(unsigned);
|
|
if (tm == 0)
|
|
return(MAJOR_06_EXCP);
|
|
ra = extru(ir, fprapos, 5) * sizeof(double)/sizeof(unsigned);
|
|
ta = extru(ir, fptapos, 5) * sizeof(double)/sizeof(unsigned);
|
|
if (ta == 0)
|
|
return(MAJOR_06_EXCP);
|
|
|
|
#ifdef TIMEX
|
|
if (ra == 0) {
|
|
/* special case FMPYCFXT */
|
|
if (dbl_fmpy(&fpregs[rm1],&fpregs[rm2],(unsigned *) &mtmp,
|
|
&status))
|
|
error = 1;
|
|
if (dbl_to_sgl_fcnvfxt(&fpregs[ta],(unsigned *) &atmp,
|
|
(unsigned *) &atmp,&status))
|
|
error = 1;
|
|
}
|
|
else {
|
|
#else
|
|
if (ra == 0)
|
|
ra = fpzeroreg;
|
|
#endif
|
|
|
|
if (dbl_fmpy(&fpregs[rm1],&fpregs[rm2],(unsigned *) &mtmp,
|
|
&status))
|
|
error = 1;
|
|
if (dbl_fadd(&fpregs[ta], &fpregs[ra], (unsigned *) &atmp,
|
|
&status))
|
|
error = 1;
|
|
#ifdef TIMEX
|
|
}
|
|
#endif
|
|
if (error)
|
|
return(MAJOR_06_EXCP);
|
|
else {
|
|
/* copy results */
|
|
fpregs[tm] = mtmp.ints.i1;
|
|
fpregs[tm+1] = mtmp.ints.i2;
|
|
fpregs[ta] = atmp.ints.i1;
|
|
fpregs[ta+1] = atmp.ints.i2;
|
|
fpregs[0] = status;
|
|
return(NOEXCEPTION);
|
|
}
|
|
}
|
|
else { /* SGL */
|
|
/*
|
|
* calculate offsets for single precision numbers
|
|
* See table 6-14 in PA-89 architecture for mapping
|
|
*/
|
|
rm1 = (extru(ir,fprm1pos,4) | 0x10 ) << 1; /* get offset */
|
|
rm1 |= extru(ir,fprm1pos-4,1); /* add right word offset */
|
|
|
|
rm2 = (extru(ir,fprm2pos,4) | 0x10 ) << 1; /* get offset */
|
|
rm2 |= extru(ir,fprm2pos-4,1); /* add right word offset */
|
|
|
|
tm = (extru(ir,fptmpos,4) | 0x10 ) << 1; /* get offset */
|
|
tm |= extru(ir,fptmpos-4,1); /* add right word offset */
|
|
|
|
ra = (extru(ir,fprapos,4) | 0x10 ) << 1; /* get offset */
|
|
ra |= extru(ir,fprapos-4,1); /* add right word offset */
|
|
|
|
ta = (extru(ir,fptapos,4) | 0x10 ) << 1; /* get offset */
|
|
ta |= extru(ir,fptapos-4,1); /* add right word offset */
|
|
|
|
if (ra == 0x20) { /* special case FMPYCFXT (really 0) */
|
|
if (sgl_fmpy(&fpregs[rm1],&fpregs[rm2],(unsigned *) &mtmp,
|
|
&status))
|
|
error = 1;
|
|
/* XXX fredette - this is broken */
|
|
#if 0
|
|
if (sgl_to_sgl_fcnvfxt(&fpregs[ta],(unsigned *) &atmp,
|
|
(unsigned *) &atmp,&status))
|
|
error = 1;
|
|
#else
|
|
panic("FMPYADD");
|
|
#endif
|
|
}
|
|
else {
|
|
if (sgl_fmpy(&fpregs[rm1],&fpregs[rm2],(unsigned *) &mtmp,
|
|
&status))
|
|
error = 1;
|
|
if (sgl_fadd(&fpregs[ta], &fpregs[ra], (unsigned *) &atmp,
|
|
&status))
|
|
error = 1;
|
|
}
|
|
if (error)
|
|
return(MAJOR_06_EXCP);
|
|
else {
|
|
/* copy results */
|
|
fpregs[tm] = mtmp.ints.i1;
|
|
fpregs[ta] = atmp.ints.i1;
|
|
fpregs[0] = status;
|
|
return(NOEXCEPTION);
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* routine to decode the 26 (FMPYSUB) instruction
|
|
*/
|
|
int
|
|
decode_26(ir,fpregs)
|
|
unsigned ir;
|
|
unsigned fpregs[];
|
|
{
|
|
unsigned rm1, rm2, tm, ra, ta; /* operands */
|
|
unsigned fmt;
|
|
unsigned error = 0;
|
|
unsigned status;
|
|
union {
|
|
double dbl;
|
|
float flt;
|
|
struct { unsigned i1; unsigned i2; } ints;
|
|
} mtmp, atmp;
|
|
|
|
|
|
status = fpregs[0];
|
|
fmt = extru(ir, fpmultifmt, 1); /* get sgl/dbl flag */
|
|
if (fmt == 0) { /* DBL */
|
|
rm1 = extru(ir, fprm1pos, 5) * sizeof(double)/sizeof(unsigned);
|
|
if (rm1 == 0)
|
|
rm1 = fpzeroreg;
|
|
rm2 = extru(ir, fprm2pos, 5) * sizeof(double)/sizeof(unsigned);
|
|
if (rm2 == 0)
|
|
rm2 = fpzeroreg;
|
|
tm = extru(ir, fptmpos, 5) * sizeof(double)/sizeof(unsigned);
|
|
if (tm == 0)
|
|
return(MAJOR_26_EXCP);
|
|
ra = extru(ir, fprapos, 5) * sizeof(double)/sizeof(unsigned);
|
|
if (ra == 0)
|
|
return(MAJOR_26_EXCP);
|
|
ta = extru(ir, fptapos, 5) * sizeof(double)/sizeof(unsigned);
|
|
if (ta == 0)
|
|
return(MAJOR_26_EXCP);
|
|
|
|
if (dbl_fmpy(&fpregs[rm1],&fpregs[rm2],(unsigned *) &mtmp,
|
|
&status))
|
|
error = 1;
|
|
if (dbl_fsub(&fpregs[ta], &fpregs[ra], (unsigned *) &atmp,
|
|
&status))
|
|
error = 1;
|
|
if (error)
|
|
return(MAJOR_26_EXCP);
|
|
else {
|
|
/* copy results */
|
|
fpregs[tm] = mtmp.ints.i1;
|
|
fpregs[tm+1] = mtmp.ints.i2;
|
|
fpregs[ta] = atmp.ints.i1;
|
|
fpregs[ta+1] = atmp.ints.i2;
|
|
fpregs[0] = status;
|
|
return(NOEXCEPTION);
|
|
}
|
|
}
|
|
else { /* SGL */
|
|
/*
|
|
* calculate offsets for single precision numbers
|
|
* See table 6-14 in PA-89 architecture for mapping
|
|
*/
|
|
rm1 = (extru(ir,fprm1pos,4) | 0x10 ) << 1; /* get offset */
|
|
rm1 |= extru(ir,fprm1pos-4,1); /* add right word offset */
|
|
|
|
rm2 = (extru(ir,fprm2pos,4) | 0x10 ) << 1; /* get offset */
|
|
rm2 |= extru(ir,fprm2pos-4,1); /* add right word offset */
|
|
|
|
tm = (extru(ir,fptmpos,4) | 0x10 ) << 1; /* get offset */
|
|
tm |= extru(ir,fptmpos-4,1); /* add right word offset */
|
|
|
|
ra = (extru(ir,fprapos,4) | 0x10 ) << 1; /* get offset */
|
|
ra |= extru(ir,fprapos-4,1); /* add right word offset */
|
|
|
|
ta = (extru(ir,fptapos,4) | 0x10 ) << 1; /* get offset */
|
|
ta |= extru(ir,fptapos-4,1); /* add right word offset */
|
|
|
|
if (sgl_fmpy(&fpregs[rm1],&fpregs[rm2],(unsigned *) &mtmp,
|
|
&status))
|
|
error = 1;
|
|
if (sgl_fsub(&fpregs[ta], &fpregs[ra], (unsigned *) &atmp,
|
|
&status))
|
|
error = 1;
|
|
if (error)
|
|
return(MAJOR_26_EXCP);
|
|
else {
|
|
/* copy results */
|
|
fpregs[tm] = mtmp.ints.i1;
|
|
fpregs[ta] = atmp.ints.i1;
|
|
fpregs[0] = status;
|
|
return(NOEXCEPTION);
|
|
}
|
|
}
|
|
|
|
}
|