257 lines
6.8 KiB
C
257 lines
6.8 KiB
C
/* $NetBSD: vtpbc.c,v 1.3 2001/06/14 18:52:27 thorpej Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Support for the V3 Semiconductor i960 PCI bus controller. This appears
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* on some MIPS boards (notably Algorithmics P-4032 and P-5064).
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*
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* Some help was provided by the Algorithmics PMON sources.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/locore.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <algor/pci/vtpbcreg.h>
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#include <algor/pci/vtpbcvar.h>
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struct vtpbc_config vtpbc_configuration;
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#define PCI_CONF_LOCK(s) (s) = splhigh()
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#define PCI_CONF_UNLOCK(s) splx((s))
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const char *vtpbc_revs[] = {
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"A",
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"B0",
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"B1",
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"B2",
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"C0",
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};
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const int vtpbc_nrevs = sizeof(vtpbc_revs) / sizeof(vtpbc_revs[0]);
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void vtpbc_attach_hook(struct device *, struct device *,
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struct pcibus_attach_args *);
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int vtpbc_bus_maxdevs(void *, int);
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pcitag_t vtpbc_make_tag(void *, int, int, int);
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void vtpbc_decompose_tag(void *, pcitag_t, int *, int *, int *);
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pcireg_t vtpbc_conf_read(void *, pcitag_t, int);
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void vtpbc_conf_write(void *, pcitag_t, int, pcireg_t);
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/*
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* vtpbc_init:
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*
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* Initialize the V3 PCI controller's software state. We
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* simply use the existing windows that the firmware has
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* set up for us.
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*/
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void
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vtpbc_init(pci_chipset_tag_t pc, struct vtpbc_config *vt)
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{
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pc->pc_conf_v = vt;
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pc->pc_attach_hook = vtpbc_attach_hook;
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pc->pc_bus_maxdevs = vtpbc_bus_maxdevs;
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pc->pc_make_tag = vtpbc_make_tag;
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pc->pc_decompose_tag = vtpbc_decompose_tag;
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pc->pc_conf_read = vtpbc_conf_read;
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pc->pc_conf_write = vtpbc_conf_write;
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vt->vt_rev = V96X_PCI_CC_REV(vt) & V96X_PCI_CC_REV_VREV;
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/*
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* Determine the PCI I/O space base that our PCI
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* I/O window maps to. NOTE: We disable this on
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* PBC rev < B2.
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*
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* Also note that PMON has disabled the I/O space
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* if the old-style PCI address map is in-use.
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*/
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if (vt->vt_rev < V96X_VREV_B2)
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vt->vt_pci_iobase = (bus_addr_t) -1;
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else {
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if ((V96X_LB_BASE2(vt) & V96X_LB_BASEx_ENABLE) == 0)
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vt->vt_pci_iobase = (bus_addr_t) -1;
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else
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vt->vt_pci_iobase =
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(V96X_LB_MAP2(vt) & V96X_LB_MAPx_MAP_ADR) << 16;
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}
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/*
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* Determine the PCI memory space base that our PCI
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* memory window maps to.
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*/
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vt->vt_pci_membase = (V96X_LB_MAP1(vt) & V96X_LB_MAPx_MAP_ADR) << 16;
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/*
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* Determine the PCI window base that maps host RAM for
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* DMA.
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*/
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vt->vt_dma_winbase = V96X_PCI_BASE1(vt) & 0xfffffff0;
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}
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void
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vtpbc_attach_hook(struct device *parent, struct device *self,
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struct pcibus_attach_args *pba)
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{
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}
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int
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vtpbc_bus_maxdevs(void *v, int busno)
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{
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return (32);
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}
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pcitag_t
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vtpbc_make_tag(void *v, int b, int d, int f)
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{
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return ((b << 16) | (d << 11) | (f << 8));
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}
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void
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vtpbc_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
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{
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if (bp != NULL)
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*bp = (tag >> 16) & 0xff;
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if (dp != NULL)
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*dp = (tag >> 11) & 0x1f;
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if (fp != NULL)
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*fp = (tag >> 8) & 0x7;
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}
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static int
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vtpbc_conf_addr(struct vtpbc_config *vt, pcitag_t tag, int offset,
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u_int32_t *cfgoff, u_int32_t *ad_low)
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{
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int b, d, f;
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vtpbc_decompose_tag(vt, tag, &b, &d, &f);
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if (b == 0) {
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if (d > (31 - vt->vt_adbase))
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return (1);
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*cfgoff = (1UL << (d + vt->vt_adbase)) | (f << 8) |
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offset;
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*ad_low = 0;
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} else if (vt->vt_rev >= V96X_VREV_C0) {
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*cfgoff = tag | offset;
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*ad_low = V96X_LB_MAPx_AD_LOW_EN;
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} else
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return (1);
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return (0);
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}
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pcireg_t
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vtpbc_conf_read(void *v, pcitag_t tag, int offset)
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{
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struct vtpbc_config *vt = v;
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pcireg_t data;
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u_int32_t cfgoff, ad_low;
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int s;
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u_int16_t errbits;
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if (vtpbc_conf_addr(vt, tag, offset, &cfgoff, &ad_low))
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return ((pcireg_t) -1);
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PCI_CONF_LOCK(s);
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/* high 12 bits of address go into map register */
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V96X_LB_MAP0(vt) = ((cfgoff >> 16) & V96X_LB_MAPx_MAP_ADR) |
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ad_low | V96X_LB_TYPE_CONF;
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/* clear aborts */
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V96X_PCI_STAT(vt) |= V96X_PCI_STAT_M_ABORT | V96X_PCI_STAT_T_ABORT;
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wbflush();
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/* low 20 bits of address are offset into config space */
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data = *(__volatile u_int32_t *) (vt->vt_cfgbase + (cfgoff & 0xfffff));
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errbits = V96X_PCI_STAT(vt) &
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(V96X_PCI_STAT_M_ABORT|V96X_PCI_STAT_T_ABORT);
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if (errbits) {
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V96X_PCI_STAT(vt) |= errbits;
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data = (pcireg_t) -1;
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}
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PCI_CONF_UNLOCK(s);
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return (data);
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}
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void
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vtpbc_conf_write(void *v, pcitag_t tag, int offset, pcireg_t data)
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{
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struct vtpbc_config *vt = v;
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u_int32_t cfgoff, ad_low;
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int s;
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if (vtpbc_conf_addr(vt, tag, offset, &cfgoff, &ad_low))
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panic("vtpbc_conf_write");
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PCI_CONF_LOCK(s);
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/* high 12 bits of address go into map register */
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V96X_LB_MAP0(vt) = ((cfgoff >> 16) & V96X_LB_MAPx_MAP_ADR) |
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ad_low | V96X_LB_TYPE_CONF;
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/* clear aborts */
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V96X_PCI_STAT(vt) |= V96X_PCI_STAT_M_ABORT | V96X_PCI_STAT_T_ABORT;
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wbflush();
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/* low 20 bits of address are offset into config space */
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*(__volatile u_int32_t *) (vt->vt_cfgbase + (cfgoff & 0xfffff)) = data;
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/* wait for FIFO to drain */
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while (V96X_FIFO_STAT(vt) & V96X_FIFO_STAT_L2P_WR)
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/* spin */ ;
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PCI_CONF_UNLOCK(s);
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}
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