556 lines
14 KiB
ArmAsm
556 lines
14 KiB
ArmAsm
/* $NetBSD: ifpga_irq.S,v 1.2 2001/10/29 14:23:35 rearnsha Exp $
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/*
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* Copyright (c) 1998 Mark Brinicombe.
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* Copyright (c) 1998 Causality Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mark Brinicombe
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* for the NetBSD Project.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include "opt_irqstats.h"
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#include "assym.h"
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#include <machine/asm.h>
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#include <machine/cpu.h>
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#include <machine/frame.h>
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#include <evbarm/ifpga/ifpgamem.h>
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#include <evbarm/ifpga/ifpgareg.h>
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.text
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.align 0
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/*
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* ffs table used for servicing irq's quickly must be here otherwise adr can't
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* reach it
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* The algorithm for ffs was devised by D. Seal and posted to
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* comp.sys.arm on 16 Feb 1994.
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*/
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.type Lirq_ffs_table, _ASM_TYPE_OBJECT;
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Lirq_ffs_table:
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/* same as ffs table but all nums are -1 from that */
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/* 0 1 2 3 4 5 6 7 */
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.byte 0, 0, 1, 12, 2, 6, 0, 13 /* 0- 7 */
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.byte 3, 0, 7, 0, 0, 0, 0, 14 /* 8-15 */
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.byte 10, 4, 0, 0, 8, 0, 0, 25 /* 16-23 */
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.byte 0, 0, 0, 0, 0, 21, 27, 15 /* 24-31 */
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.byte 31, 11, 5, 0, 0, 0, 0, 0 /* 32-39 */
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.byte 9, 0, 0, 24, 0, 0, 20, 26 /* 40-47 */
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.byte 30, 0, 0, 0, 0, 23, 0, 19 /* 48-55 */
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.byte 29, 0, 22, 18, 28, 17, 16, 0 /* 56-63 */
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/*
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*
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* irq_entry
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*
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* Main entry point for the IRQ vector
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*
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* This function reads the IRQ request register in the 21285
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* and then calls the installed handlers for each bit that is set.
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* The function stray_irqhandler is called if a handler is not defined
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* for a particular interrupt.
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* If a interrupt handler is found then it is called with r0 containing
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* the argument defined in the handler structure. If the field ih_arg
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* is zero then a pointer to the IRQ frame on the stack is passed instead.
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*/
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Lintr_disabled_mask:
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.word _C_LABEL(intr_disabled_mask)
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Lintr_claimed_mask:
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.word _C_LABEL(intr_claimed_mask)
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Lcurrent_spl_level:
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.word _C_LABEL(current_spl_level)
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Lcurrent_intr_depth:
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.word _C_LABEL(current_intr_depth)
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.word _C_LABEL(prev_intr_depth)
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Lspl_masks:
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.word _C_LABEL(spl_masks)
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Lirq_vbase:
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.word _C_LABEL(ifpga_irq_vbase)
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/*
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* Register usage
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*
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* r5 - Address of ffs table
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* r6 - Address of current handler
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* r7 - Pointer to handler pointer list
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* r8 - Current IRQ requests.
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* r10 - Base address of IOMD
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* r11 - IRQ requests still to service.
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*/
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ASENTRY_NP(irq_entry)
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sub lr, lr, #0x00000004 /* Adjust the lr */
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PUSHFRAMEINSVC /* Push an interrupt frame */
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/*
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* Note that we have entered the IRQ handler.
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* We are in SVC mode so we cannot use the processor mode
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* to determine if we are in an IRQ. Instead we will count the
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* each time the interrupt handler is nested.
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*/
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ldr r0, Lcurrent_intr_depth
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ldr r2, Lcurrent_intr_depth+4
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ldr r1, [r0]
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str r1, [r2]
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add r1, r1, #1
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str r1, [r0]
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/* Load r8 with the IFPGA interrupt requests */
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ldr r10, Lirq_vbase
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ldr r10, [r10]
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ldr r8, [r10, #(IFPGA_INTR_STATUS)]
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/* This condition needs further examination */
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teq r8, #0
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beq irq_unknown
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/* Block the current requested interrupts */
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ldr r1, Lintr_disabled_mask
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ldr r0, [r1]
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stmfd sp!, {r0}
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orr r0, r0, r8
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/*
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* Need to block all interrupts at the IPL or lower for
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* all asserted interrupts.
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* This basically emulates hardware interrupt priority levels.
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* Means we need to go through the interrupt mask and for
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* every asserted interrupt we need to mask out all other
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* interrupts at the same or lower IPL.
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* If only we could wait until the main loop but we need to sort
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* this out first so interrupts can be re-enabled.
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*
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* This would benefit from a special ffs type routine
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*/
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mov r9, #(_SPL_LEVELS - 1)
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ldr r7, Lspl_masks
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Lfind_highest_ipl:
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ldr r2, [r7, r9, lsl #2]
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tst r8, r2
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subeq r9, r9, #1
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beq Lfind_highest_ipl
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/* r9 = SPL level of highest priority interrupt */
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add r9, r9, #1
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ldr r2, [r7, r9, lsl #2]
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mvn r2, r2
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orr r0, r0, r2
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str r0, [r1] /* store new disabled mask */
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ldr r2, Lcurrent_spl_level
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ldr r1, [r2]
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str r9, [r2]
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stmfd sp!, {r1}
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ldr r7, Lintr_claimed_mask /* get claimed mask */
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ldr r6, [r7]
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bic r6, r6, r0 /* mask out disabled */
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ldr r7, Lintr_current_mask /* get claimed mask */
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str r6, [r7] /* new current mask */
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ldr r7, Lirq_vbase
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/* Update the IFPGA irq masks */
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bl _C_LABEL(irq_setmasks_nointr)
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ldr r7, [r7] /* Ensure irq pin has time to update */
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Lstill_pending:
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ldr r0, [r7, #(IFPGA_INTR_STATUS)]
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tst r0, r8
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bne Lstill_pending
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mrs r0, cpsr_all /* Enable IRQ's */
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bic r0, r0, #I32_bit
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msr cpsr_all, r0
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ldr r7, Lirqhandlers
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/* take a copy of the irq mask so we can alter it */
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mov r11, r8
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/* ffs routine to find first irq to service */
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/* standard trick to isolate bottom bit in a0 or 0 if a0 = 0 on entry */
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rsb r4, r11, #0
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ands r10, r11, r4
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/*
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* now r10 has at most 1 set bit, call this X
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* if X = 0, branch to exit code
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*/
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beq exitirq
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adr r5, Lirq_ffs_table
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irqloop:
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/*
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* at this point:
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* r5 = address of ffs table
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* r7 = address of irq handlers table
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* r8 = irq request
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* r10 = bit of irq to be serviced
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* r11 = bitmask of IRQ's to service
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*/
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/* find the set bit */
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orr r9, r10, r10, lsl #4 /* X * 0x11 */
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orr r9, r9, r9, lsl #6 /* X * 0x451 */
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rsb r9, r9, r9, lsl #16 /* X * 0x0450fbaf */
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/* fetch the bit number */
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ldrb r9, [r5, r9, lsr #26 ]
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/*
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* r9 = irq to service
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*/
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/* apologies for the dogs dinner of code here, but it's in an attempt
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* to minimise stalling on SA's, hence lots of things happen here:
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* - getting address of handler, if it doesn't exist we call
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* stray_irqhandler this is assumed to be rare so we don't
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* care about performance for it
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* - statinfo is updated
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* - unsetting of the irq bit in r11
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* - irq stats (if enabled) also get put in the mix
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*/
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ldr r4, Lcnt /* Stat info A */
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ldr r6, [r7, r9, lsl #2] /* Get address of first handler structure */
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ldr r1, [r4, #(V_INTR)] /* Stat info B */
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teq r6, #0x00000000 /* Do we have a handler */
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moveq r0, r8 /* IRQ requests as arg 0 */
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addeq lr, pc, #nextirq - . - 8 /* return address */
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bic r11, r11, r10 /* clear the IRQ bit */
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beq _C_LABEL(stray_irqhandler) /* call special handler */
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#ifdef IRQSTATS
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ldr r2, Lintrcnt
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ldr r3, [r6, #(IH_NUM)]
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#endif
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/* stat info C */
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add r1, r1, #0x00000001
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#ifdef IRQSTATS
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ldr r3, [r2, r3, lsl #2]!
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#endif
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/* stat info D */
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str r1, [r4, #(V_INTR)]
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#ifdef IRQSTATS
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add r3, r3, #0x00000001
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str r3, [r2]
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#endif /* IRQSTATS */
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irqchainloop:
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ldr r0, [r6, #(IH_ARG)] /* Get argument pointer */
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add lr, pc, #nextinchain - . - 8 /* return address */
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teq r0, #0x00000000 /* If arg is zero pass stack frame */
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addeq r0, sp, #8 /* ... stack frame [XXX needs care] */
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ldr pc, [r6, #(IH_FUNC)] /* Call handler */
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nextinchain:
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ldr r6, [r6, #(IH_NEXT)] /* fetch next handler */
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#if 0
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teq r0, #0x00000001 /* Was the irq serviced ? */
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#endif
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/* if it was it'll just fall through this: */
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teq r6, #0x00000000
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bne irqchainloop
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nextirq:
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/* Check for next irq */
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rsb r4, r11, #0
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ands r10, r11, r4
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/* check if there are anymore irq's to service */
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bne irqloop
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exitirq:
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ldmfd sp!, {r2, r3}
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ldr r1, Lcurrent_spl_level
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ldr r9, Lintr_disabled_mask
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ldr r7, Lspl_masks
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ldr r8, Lspl_mask
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ldr r7, [r7, r2, lsl #2] /* Mask for new spl level */
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str r2, [r1] /* store current spl level */
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str r7, [r8] /* Restore the spl_mask */
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ldr r1, Lintr_claimed_mask /* get claimed mask */
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str r3, [r9] /* store disabled mask */
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ldr r0, [r1]
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ldr r9, Lintr_current_mask /* get claimed mask */
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bic r0, r0, r3 /* mask out disabled */
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str r0, [r9] /* new current mask */
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bl _C_LABEL(irq_setmasks)
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bl _C_LABEL(dosoftints) /* Handle the soft interrupts */
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/* Manage AST's. Maybe this should be done as a soft interrupt ? */
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ldr r0, [sp] /* Get the SPSR from stack */
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and r0, r0, #(PSR_MODE) /* Test for USR32 mode before the IRQ */
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teq r0, #(PSR_USR32_MODE)
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ldreq r0, Lastpending /* Do we have an AST pending ? */
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ldreq r1, [r0]
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teqeq r1, #0x00000001
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beq irqast /* call the AST handler */
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/* Kill IRQ's in preparation for exit */
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mrs r0, cpsr_all
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orr r0, r0, #(I32_bit)
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msr cpsr_all, r0
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irq_unknown:
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/* Decrement the nest count */
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ldr r0, Lcurrent_intr_depth
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ldr r2, Lcurrent_intr_depth+4
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ldr r1, [r0]
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str r1, [r2]
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sub r1, r1, #1
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str r1, [r0]
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PULLFRAMEFROMSVCANDEXIT
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movs pc, lr /* Exit */
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/*
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* Ok, snag with current intr depth ...
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* If ast() calls mi_sleep() the current_intr_depth will not be
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* decremented until the process is woken up. This can result
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* in the system believing it is still in the interrupt handler.
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* If we are calling ast() then correct the current_intr_depth
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* before the call.
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*/
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irqast:
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mov r1, #0x00000000 /* Clear ast_pending */
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str r1, [r0]
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/* Kill IRQ's so we atomically decrement current_intr_depth */
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mrs r2, cpsr_all
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orr r3, r2, #(I32_bit)
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msr cpsr_all, r3
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/* Decrement the nest count */
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ldr r0, Lcurrent_intr_depth
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ldr r4, Lcurrent_intr_depth+4
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ldr r1, [r0]
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str r1, [r4]
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sub r1, r1, #1
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str r1, [r0]
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/* Restore IRQ's */
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msr cpsr_all, r2
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mov r0, sp
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bl _C_LABEL(ast)
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/* Kill IRQ's in preparation for exit */
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mrs r0, cpsr_all
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orr r0, r0, #(I32_bit)
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msr cpsr_all, r0
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PULLFRAMEFROMSVCANDEXIT
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movs pc, lr /* Exit */
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Lcnt:
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.word _C_LABEL(uvmexp)
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Lintrcnt:
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.word _C_LABEL(intrcnt)
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Lirqhandlers:
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.word _C_LABEL(irqhandlers) /* Pointer to array of irqhandlers */
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Lastpending:
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.word _C_LABEL(astpending)
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Lspl_mask:
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.word _C_LABEL(spl_mask) /* irq's allowed at current spl level */
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Lintr_current_mask:
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.word _C_LABEL(intr_current_mask)
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ENTRY(irq_setmasks)
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/* Disable interrupts */
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mrs r3, cpsr_all
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orr r1, r3, #(I32_bit)
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msr cpsr_all, r1
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/* Calculate IFPGA interrupt mask */
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ldr r1, Lintr_current_mask /* All the enabled interrupts */
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ldr r2, Lspl_mask /* Block due to current spl level */
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ldr r0, Lirq_vbase /* Virtual address of irq ctrlr */
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ldr r1, [r1]
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ldr r2, [r2]
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ldr r0, [r0]
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and r1, r1, r2
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str r1, [r0, #(IFPGA_INTR_ENABLESET)]
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mvn r1, r1
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str r1, [r0, #(IFPGA_INTR_ENABLECLR)]
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/* Restore old cpsr and exit */
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msr cpsr_all, r3
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mov pc, lr
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ENTRY(irq_setmasks_nointr)
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/* Calculate IFPGA interrupt mask */
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ldr r1, Lintr_current_mask /* All the enabled interrupts */
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ldr r2, Lspl_mask /* Block due to current spl level */
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ldr r0, Lirq_vbase
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ldr r1, [r1]
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ldr r2, [r2]
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ldr r0, [r0]
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and r1, r1, r2
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str r1, [r0, #(IFPGA_INTR_ENABLESET)]
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mvn r1, r1
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str r1, [r0, #(IFPGA_INTR_ENABLECLR)]
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mov pc, lr
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.data
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.align 0
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.global _C_LABEL(prev_intr_depth)
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_C_LABEL(prev_intr_depth):
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.word 0
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#ifdef IRQSTATS
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/* These symbols are used by vmstat */
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.text
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.global _C_LABEL(_intrnames)
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_C_LABEL(_intrnames):
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.word _C_LABEL(intrnames)
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.data
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.align 0
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.global _C_LABEL(intrnames), _C_LABEL(sintrnames), _C_LABEL(eintrnames)
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.global _C_LABEL(intrcnt), _C_LABEL(sintrcnt), _C_LABEL(eintrcnt)
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_C_LABEL(intrnames):
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.asciz "interrupt 0 "
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.asciz "interrupt 1 "
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.asciz "interrupt 2 "
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.asciz "interrupt 3 "
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.asciz "interrupt 4 "
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.asciz "interrupt 5 "
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.asciz "interrupt 6 "
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.asciz "interrupt 7 "
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.asciz "interrupt 8 "
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.asciz "interrupt 9 "
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.asciz "interrupt 10 "
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.asciz "interrupt 11 "
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.asciz "interrupt 12 "
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.asciz "interrupt 13 "
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.asciz "interrupt 14 "
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.asciz "interrupt 15 "
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.asciz "interrupt 16 "
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.asciz "interrupt 17 "
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.asciz "interrupt 18 "
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.asciz "interrupt 19 "
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.asciz "interrupt 20 "
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.asciz "interrupt 21 "
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.asciz "interrupt 22 "
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.asciz "interrupt 23 "
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.asciz "interrupt 24 "
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.asciz "interrupt 25 "
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.asciz "interrupt 26 "
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.asciz "interrupt 27 "
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.asciz "interrupt 28 "
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.asciz "interrupt 29 "
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.asciz "interrupt 30 "
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.asciz "interrupt 31 "
|
|
_C_LABEL(sintrnames):
|
|
.asciz "soft int 0 "
|
|
.asciz "soft int 1 "
|
|
.asciz "soft int 2 "
|
|
.asciz "soft int 3 "
|
|
.asciz "soft int 4 "
|
|
.asciz "soft int 5 "
|
|
.asciz "soft int 6 "
|
|
.asciz "soft int 7 "
|
|
.asciz "soft int 8 "
|
|
.asciz "soft int 9 "
|
|
.asciz "soft int 10 "
|
|
.asciz "soft int 11 "
|
|
.asciz "soft int 12 "
|
|
.asciz "soft int 13 "
|
|
.asciz "soft int 14 "
|
|
.asciz "soft int 15 "
|
|
.asciz "soft int 16 "
|
|
.asciz "soft int 17 "
|
|
.asciz "soft int 18 "
|
|
.asciz "soft int 19 "
|
|
.asciz "soft int 20 "
|
|
.asciz "soft int 21 "
|
|
.asciz "soft int 22 "
|
|
.asciz "soft int 23 "
|
|
.asciz "soft int 24 "
|
|
.asciz "soft int 25 "
|
|
.asciz "soft int 26 "
|
|
.asciz "soft int 27 "
|
|
.asciz "soft int 28 "
|
|
.asciz "soft int 29 "
|
|
.asciz "soft int 30 "
|
|
.asciz "soft int 31 "
|
|
_C_LABEL(eintrnames):
|
|
|
|
.bss
|
|
.align 0
|
|
.global _C_LABEL(intrcnt), _C_LABEL(sintrcnt), _C_LABEL(eintrcnt)
|
|
_C_LABEL(intrcnt):
|
|
.space 32*4 /* XXX Should be linked to number of interrupts */
|
|
_C_LABEL(sintrcnt):
|
|
.space 32*4 /* XXX Should be linked to number of soft ints */
|
|
_C_LABEL(eintrcnt):
|
|
|
|
#else /* IRQSTATS */
|
|
/* Dummy entries to keep vmstat happy */
|
|
|
|
.text
|
|
.globl _C_LABEL(intrnames), _C_LABEL(eintrnames), _C_LABEL(intrcnt), _C_LABEL(eintrcnt)
|
|
_C_LABEL(intrnames):
|
|
.long 0
|
|
_C_LABEL(eintrnames):
|
|
|
|
_C_LABEL(intrcnt):
|
|
.long 0
|
|
_C_LABEL(eintrcnt):
|
|
#endif /* IRQSTATS */
|
|
|