108 lines
5.0 KiB
C
108 lines
5.0 KiB
C
/* $NetBSD: pciide_natsemi_reg.h,v 1.1 2010/11/10 22:34:24 skrll Exp $ */
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/* $OpenBSD: pciide_natsemi_reg.h,v 1.7 2007/06/24 12:41:19 kettenis Exp $ */
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/*
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* Copyright (c) 2001 Jason L. Wright (jason@thought.net)
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* Copyright (c) 2004 Alexander Yurchenko <grange@openbsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_PCI_PCIIDE_NATSEMI_REG_H_
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#define _DEV_PCI_PCIIDE_NATSEMI_REG_H_
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/*
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* Register definitions for National Semiconductor PC87415. Definitions
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* based on "PC87415: PCI-IDE DMA Master Mode Interface Controller"
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* (March 1996) datasheet from their website.
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*/
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#define NATSEMI_CTRL1 0x40 /* Control register1 */
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#define NATSEMI_CTRL1_SWRST 0x04 /* sw rst to ch1/ch2 on */
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#define NATSEMI_CTRL1_IDEPWR 0x08
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#define NATSEMI_CTRL1_CH1INTMAP 0x10
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#define NATSEMI_CTRL1_CH2INTMAP 0x20
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#define NATSEMI_CTRL1_INTAMASK 0x40
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#define NATSEMI_CTRL1_IDWR 0x80 /* write to did/vid enable */
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#define NATSEMI_CTRL2 0x41 /* Control register2 */
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#define NATSEMI_CTRL2_CH1MASK 0x01 /* channel 1 intr masked */
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#define NATSEMI_CTRL2_CH2MASK 0x02 /* channel 2 intr masked */
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#define NATSEMI_CTRL2_BARDIS 0x04 /* PCI BAR 2/3 disable */
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#define NATSEMI_CTRL2_WATCHDOG 0x08 /* enable watchdog timer */
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#define NATSEMI_CTRL2_BUF1BYP 0x10 /* bypass buffer 1 */
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#define NATSEMI_CTRL2_BUF2BYP 0x20 /* bypass buffer 2 */
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#define NATSEMI_CTRL2_IDE1MAP 0x40 /* IDE at bar 1 */
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#define NATSEMI_CTRL2_IDE2MAP 0x80 /* IDE at bar 2 */
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#define NATSEMI_CHMASK(chn) (NATSEMI_CTRL2_CH1MASK << (chn))
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#define NATSEMI_CTRL3 0x42 /* Control register3 */
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#define NATSEMI_CTRL3_CH1PREDIS 0x01 /* channel 1 prefetch disable */
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#define NATSEMI_CTRL3_CH2PREDIS 0x02 /* channel 2 prefetch disable */
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#define NATSEMI_CTRL3_RSTIDLE 0x04 /* reset idle state */
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#define NATSEMI_CTRL3_C1D1DMARQ 0x10 /* c1d1 dmarq handshaking */
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#define NATSEMI_CTRL3_C1D2DMARQ 0x20 /* c1d2 dmarq handshaking */
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#define NATSEMI_CTRL3_C2D1DMARQ 0x40 /* c2d1 dmarq handshaking */
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#define NATSEMI_CTRL3_C2D2DMARQ 0x80 /* c2d2 dmarq handshaking */
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#define NATSEMI_WBS 0x43 /* Write buffer status */
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#define NATSEMI_WBS_WB1NMPTY 0x01 /* chan 1 write buf not empty */
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#define NATSEMI_WBS_WB2NMPTY 0x02 /* chan 2 write buf not empty */
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#define NATSEMI_C1D1DRT 0x44 /* Channel 1/device 1 data read timing */
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#define NATSEMI_C1D1DWT 0x45 /* Channel 1/device 1 data write timing */
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#define NATSEMI_C1D2DRT 0x48 /* Channel 1/device 2 data read timing */
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#define NATSEMI_C1D2DWT 0x49 /* Channel 1/device 2 data write timing */
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#define NATSEMI_C2D1DRT 0x4c /* Channel 2/device 1 data read timing */
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#define NATSEMI_C2D1DWT 0x4d /* Channel 2/device 1 data write timing */
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#define NATSEMI_C2D2DRT 0x50 /* Channel 2/device 2 data read timing */
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#define NATSEMI_C2D2DWT 0x51 /* Channel 2/device 2 data write timing */
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#define NATSEMI_CCBT 0x54 /* Command and control block timing */
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#define NATSEMI_SECT 0x55 /* Sector size */
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#define NATSEMI_SECT_C1UNUSED 0x0f /* not used */
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#define NATSEMI_SECT_C1_512 0x0e /* 512 bytes */
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#define NATSEMI_SECT_C1_1024 0x0c /* 1024 bytes */
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#define NATSEMI_SECT_C1_2048 0x08 /* 2048 bytes */
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#define NATSEMI_SECT_C1_4096 0x00 /* 4096 bytes */
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#define NATSEMI_SECT_C2UNUSED 0xf0 /* not used */
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#define NATSEMI_SECT_C2_512 0xe0 /* 512 bytes */
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#define NATSEMI_SECT_C2_1024 0xc0 /* 1024 bytes */
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#define NATSEMI_SECT_C2_2048 0x80 /* 2048 bytes */
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#define NATSEMI_SECT_C2_4096 0x00 /* 4096 bytes */
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#define NATSEMI_RTREG(c,d) (0x44 + (c * 8) + (d * 4) + 0)
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#define NATSEMI_WTREG(c,d) (0x44 + (c * 8) + (d * 4) + 1)
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/* 17 - N = number of clocks */
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static u_int8_t natsemi_pio_pulse[] = { 7, 12, 13, 14, 14 };
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static u_int8_t natsemi_dma_pulse[] = { 7, 10, 10 };
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/* 16 - N = number of clocks */
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static u_int8_t natsemi_pio_recover[] = { 6, 8, 11, 13, 15 };
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static u_int8_t natsemi_dma_recover[] = { 6, 8, 9 };
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#endif /* !_DEV_PCI_PCIIDE_NATSEMI_REG_H_ */
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