463 lines
12 KiB
C
463 lines
12 KiB
C
/* $NetBSD: iwic_dchan.c,v 1.7 2012/10/27 17:18:34 chs Exp $ */
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/*
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* Copyright (c) 1999, 2000 Dave Boyce. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*---------------------------------------------------------------------------
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*
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* i4b_iwic - isdn4bsd Winbond W6692 driver
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* ----------------------------------------
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*
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* $FreeBSD$
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*
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* last edit-date: [Tue Jan 16 13:20:14 2001]
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*
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*---------------------------------------------------------------------------*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: iwic_dchan.c,v 1.7 2012/10/27 17:18:34 chs Exp $");
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/mbuf.h>
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#include <sys/callout.h>
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#include <net/if.h>
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#include <sys/bus.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/iwicreg.h>
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#include <dev/pci/iwicvar.h>
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#include <netisdn/i4b_global.h>
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#include <netisdn/i4b_mbuf.h>
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#define MAX_DFRAME_LEN 264
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static void dchan_receive(struct iwic_softc *sc, int ista);
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/*---------------------------------------------------------------------------*
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* initialize D-channel variables and registers
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*---------------------------------------------------------------------------*/
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void
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iwic_dchan_init(struct iwic_softc *sc)
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{
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sc->sc_dchan.ibuf = NULL;
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sc->sc_dchan.rx_count = 0;
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sc->sc_dchan.obuf = NULL;
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sc->sc_dchan.obuf2 = NULL;
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sc->sc_dchan.tx_count = 0;
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sc->sc_dchan.tx_ready = 0;
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IWIC_WRITE(sc, D_CTL, D_CTL_SRST);
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DELAY(5000);
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IWIC_WRITE(sc, D_CTL, 0);
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IWIC_WRITE(sc, SQX, SQX_SCIE);
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IWIC_WRITE(sc, PCTL, 0x00);
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IWIC_WRITE(sc, MOCR, 0x00);
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IWIC_WRITE(sc, GCR, 0x00);
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IWIC_WRITE(sc, D_CMDR, D_CMDR_RRST | D_CMDR_XRST);
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IWIC_WRITE(sc, D_MODE, D_MODE_RACT);
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IWIC_WRITE(sc, D_SAM, 0xff);
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IWIC_WRITE(sc, D_TAM, 0xff);
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IWIC_WRITE(sc, D_EXIM, 0x00);
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}
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/*---------------------------------------------------------------------------*
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* Extended IRQ handler for the D-channel
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*---------------------------------------------------------------------------*/
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void
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iwic_dchan_xirq(struct iwic_softc *sc)
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{
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int irq_stat;
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int stat;
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irq_stat = IWIC_READ(sc, D_EXIR);
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if (irq_stat & D_EXIR_RDOV)
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{
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NDBGL1(L1_I_ERR, "RDOV in state %s", iwic_printstate(sc));
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IWIC_WRITE(sc, D_CMDR, D_CMDR_RRST);
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}
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if (irq_stat & D_EXIR_XDUN)
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{
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NDBGL1(L1_I_ERR, "XDUN in state %s", iwic_printstate(sc));
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sc->sc_dchan.tx_ready = 0;
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}
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if (irq_stat & D_EXIR_XCOL)
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{
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NDBGL1(L1_I_ERR, "XCOL in state %s", iwic_printstate(sc));
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IWIC_WRITE(sc, D_CMDR, D_CMDR_XRST);
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sc->sc_dchan.tx_ready = 0;
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}
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if (irq_stat & D_EXIR_TIN2)
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{
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NDBGL1(L1_I_ERR, "TIN2 in state %s", iwic_printstate(sc));
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}
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if (irq_stat & D_EXIR_MOC)
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{
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stat = IWIC_READ(sc, MOR);
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NDBGL1(L1_I_ERR, "MOC in state %s, byte = 0x%x", iwic_printstate(sc), stat);
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}
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if (irq_stat & D_EXIR_ISC)
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{
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stat = (IWIC_READ(sc, CIR)) & 0x0f;
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switch (stat)
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{
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case CIR_CE:
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NDBGL1(L1_I_CICO, "rx CE in state %s", iwic_printstate(sc));
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iwic_next_state(sc, EV_CE);
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break;
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case CIR_DRD:
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NDBGL1(L1_I_CICO, "rx DRD in state %s", iwic_printstate(sc));
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iwic_next_state(sc, EV_INFO0);
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isdn_layer2_status_ind(&sc->sc_l2, sc->sc_l3token, STI_L1STAT, LAYER_IDLE);
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break;
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case CIR_LD:
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NDBGL1(L1_I_CICO, "rx LD in state %s", iwic_printstate(sc));
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iwic_next_state(sc, EV_RSY);
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break;
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case CIR_ARD:
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NDBGL1(L1_I_CICO, "rx ARD in state %s", iwic_printstate(sc));
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iwic_next_state(sc, EV_INFO2);
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break;
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case CIR_TI:
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NDBGL1(L1_I_CICO, "rx TI in state %s", iwic_printstate(sc));
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iwic_next_state(sc, EV_INFO0);
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break;
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case CIR_ATI:
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NDBGL1(L1_I_CICO, "rx ATI in state %s", iwic_printstate(sc));
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iwic_next_state(sc, EV_INFO0);
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break;
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case CIR_AI8:
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NDBGL1(L1_I_CICO, "rx AI8 in state %s", iwic_printstate(sc));
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isdn_layer2_status_ind(&sc->sc_l2, sc->sc_l3token, STI_L1STAT, LAYER_ACTIVE);
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iwic_next_state(sc, EV_INFO48);
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break;
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case CIR_AI10:
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NDBGL1(L1_I_CICO, "rx AI10 in state %s", iwic_printstate(sc));
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isdn_layer2_status_ind(&sc->sc_l2, sc->sc_l3token, STI_L1STAT, LAYER_ACTIVE);
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iwic_next_state(sc, EV_INFO410);
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break;
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case CIR_CD:
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NDBGL1(L1_I_CICO, "rx DIS in state %s", iwic_printstate(sc));
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iwic_next_state(sc, EV_DIS);
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break;
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default:
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NDBGL1(L1_I_ERR, "ERROR, unknown indication 0x%x in state %s", stat, iwic_printstate(sc));
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iwic_next_state(sc, EV_INFO0);
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break;
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}
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}
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if (irq_stat & D_EXIR_TEXP)
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{
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NDBGL1(L1_I_ERR, "TEXP in state %s", iwic_printstate(sc));
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}
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if (irq_stat & D_EXIR_WEXP)
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{
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NDBGL1(L1_I_ERR, "WEXP in state %s", iwic_printstate(sc));
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}
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}
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/*---------------------------------------------------------------------------*
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* All receiving and transmitting takes place here.
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*---------------------------------------------------------------------------*/
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void
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iwic_dchan_xfer_irq(struct iwic_softc *sc, int ista)
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{
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NDBGL1(L1_I_MSG, "ISTA = 0x%x", ista);
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if (ista & (ISTA_D_RMR | ISTA_D_RME))
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{
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/* Receive message ready */
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dchan_receive(sc, ista);
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}
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if (ista & ISTA_D_XFR)
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{
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/* Transmitter ready */
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sc->sc_dchan.tx_ready = 1;
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iwic_dchan_transmit(sc);
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}
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}
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/*---------------------------------------------------------------------------*
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* disable D-channel
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*---------------------------------------------------------------------------*/
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void
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iwic_dchan_disable(struct iwic_softc *sc)
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{
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int s;
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s = splnet();
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if (sc->sc_dchan.obuf)
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{
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if (sc->sc_dchan.free_obuf)
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i4b_Dfreembuf(sc->sc_dchan.obuf);
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sc->sc_dchan.obuf = NULL;
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}
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if (sc->sc_dchan.obuf2)
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{
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if (sc->sc_dchan.free_obuf2)
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i4b_Dfreembuf(sc->sc_dchan.obuf2);
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sc->sc_dchan.obuf2 = NULL;
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}
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splx(s);
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IWIC_WRITE(sc, CIX, CIX_DRC);
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}
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/*---------------------------------------------------------------------------*
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* queue D-channel message for transmission
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*---------------------------------------------------------------------------*/
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int
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iwic_dchan_data_req(struct iwic_softc *sc, struct mbuf *m, int freeflag)
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{
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int s;
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if (!m)
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return 0;
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s = splnet();
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/* Queue message */
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if (sc->sc_dchan.obuf)
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{
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if (sc->sc_dchan.obuf2)
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{
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NDBGL1(L1_I_ERR, "no buffer space!");
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}
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else
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{
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sc->sc_dchan.obuf2 = m;
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sc->sc_dchan.free_obuf2 = freeflag;
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}
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}
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else
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{
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sc->sc_dchan.obuf = m;
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sc->sc_dchan.obuf_ptr = m->m_data;
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sc->sc_dchan.obuf_len = m->m_len;
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sc->sc_dchan.free_obuf = freeflag;
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}
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iwic_dchan_transmit(sc);
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splx(s);
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return (0);
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}
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/*---------------------------------------------------------------------------*
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* allocate an mbuf
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*---------------------------------------------------------------------------*/
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static void
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dchan_get_mbuf(struct iwic_softc *sc, int len)
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{
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sc->sc_dchan.ibuf = i4b_Dgetmbuf(len);
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if (!sc->sc_dchan.ibuf)
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panic("dchan_get_mbuf: unable to allocate %d bytes for mbuf!", len);
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sc->sc_dchan.ibuf_ptr = sc->sc_dchan.ibuf->m_data;
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sc->sc_dchan.ibuf_max_len = sc->sc_dchan.ibuf->m_len;
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sc->sc_dchan.ibuf_len = 0;
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}
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/*---------------------------------------------------------------------------*
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* D-channel receive data interrupt
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*---------------------------------------------------------------------------*/
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static void
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dchan_receive(struct iwic_softc *sc, int ista)
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{
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int command = D_CMDR_RACK;
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if (ista & ISTA_D_RMR)
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{
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/* Got 64 bytes in FIFO */
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if (!sc->sc_dchan.ibuf)
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{
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dchan_get_mbuf(sc, MAX_DFRAME_LEN);
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}
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else if ((sc->sc_dchan.ibuf_len + MAX_DFRAME_LEN) >
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sc->sc_dchan.ibuf_max_len)
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{
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panic("dchan_receive: not enough space in buffer!");
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}
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IWIC_RDDFIFO(sc, sc->sc_dchan.ibuf_ptr, 64);
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sc->sc_dchan.ibuf_ptr += 64;
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sc->sc_dchan.ibuf_len += 64;
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sc->sc_dchan.rx_count += 64;
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}
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if (ista & ISTA_D_RME)
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{
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/* Got end of frame */
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int status;
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status = IWIC_READ(sc, D_RSTA);
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if (status & (D_RSTA_RDOV | D_RSTA_CRCE | D_RSTA_RMB))
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{
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if (status & D_RSTA_RDOV)
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NDBGL1(L1_I_ERR, "%s: D-channel Receive Data Overflow", device_xname(sc->sc_dev));
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if (status & D_RSTA_CRCE)
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NDBGL1(L1_I_ERR, "%s: D-channel CRC Error", device_xname(sc->sc_dev));
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if (status & D_RSTA_RMB)
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NDBGL1(L1_I_ERR, "%s: D-channel Receive Message Aborted", device_xname(sc->sc_dev));
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command |= D_CMDR_RRST;
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}
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else
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{
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int hi, lo;
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int total_frame_len;
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lo = IWIC_READ(sc, D_RBCL);
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hi = IWIC_READ(sc, D_RBCH);
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total_frame_len = D_RBC(hi, lo);
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lo = lo & 0x3f;
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if (lo == 0)
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lo = IWIC_DCHAN_FIFO_LEN;
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if (!sc->sc_dchan.ibuf)
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{
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dchan_get_mbuf(sc, lo);
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}
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else if ((sc->sc_dchan.ibuf_len + lo) >
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sc->sc_dchan.ibuf_max_len)
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{
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panic("dchan_receive: buffer not long enough");
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}
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IWIC_RDDFIFO(sc, sc->sc_dchan.ibuf_ptr, lo);
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sc->sc_dchan.ibuf_len += lo;
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sc->sc_dchan.rx_count += lo;
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sc->sc_dchan.ibuf->m_len = sc->sc_dchan.ibuf_len;
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if(sc->sc_trace & TRACE_D_RX)
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{
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i4b_trace_hdr hdr;
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hdr.type = TRC_CH_D;
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hdr.dir = FROM_NT;
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hdr.count = ++sc->sc_dchan.trace_count;
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isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, sc->sc_dchan.ibuf->m_len, sc->sc_dchan.ibuf->m_data);
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}
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isdn_layer2_data_ind(&sc->sc_l2,sc->sc_l3token,sc->sc_dchan.ibuf);
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sc->sc_dchan.ibuf = NULL;
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}
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}
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IWIC_WRITE(sc, D_CMDR, command);
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}
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/*---------------------------------------------------------------------------*
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* transmit D-channel frame
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*---------------------------------------------------------------------------*/
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void
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iwic_dchan_transmit(struct iwic_softc *sc)
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{
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int cmd;
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u_char *ptr;
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int len;
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if (!sc->sc_dchan.tx_ready)
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return;
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if (!sc->sc_dchan.obuf)
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return;
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if (sc->sc_I430state != ST_F7)
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return;
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ptr = sc->sc_dchan.obuf_ptr;
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len = min(sc->sc_dchan.obuf_len, IWIC_DCHAN_FIFO_LEN);
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if(sc->sc_trace & TRACE_D_TX)
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{
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i4b_trace_hdr hdr;
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hdr.type = TRC_CH_D;
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hdr.dir = FROM_TE;
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hdr.count = ++sc->sc_dchan.trace_count;
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isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, len, ptr);
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}
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IWIC_WRDFIFO(sc, ptr, len);
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sc->sc_dchan.tx_count += len;
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if (len < sc->sc_dchan.obuf_len)
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{
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sc->sc_dchan.obuf_ptr += len;
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sc->sc_dchan.obuf_len -= len;
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cmd = D_CMDR_XMS;
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}
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else
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{
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if (sc->sc_dchan.free_obuf)
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i4b_Dfreembuf(sc->sc_dchan.obuf);
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sc->sc_dchan.obuf = NULL;
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sc->sc_dchan.obuf_ptr = NULL;
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sc->sc_dchan.obuf_len = 0;
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if (sc->sc_dchan.obuf2)
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{
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sc->sc_dchan.obuf = sc->sc_dchan.obuf2;
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sc->sc_dchan.obuf_ptr = sc->sc_dchan.obuf->m_data;
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sc->sc_dchan.obuf_len = sc->sc_dchan.obuf->m_len;
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sc->sc_dchan.free_obuf = sc->sc_dchan.free_obuf2;
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sc->sc_dchan.obuf2 = NULL;
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}
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cmd = D_CMDR_XMS | D_CMDR_XME;
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}
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sc->sc_dchan.tx_ready = 0;
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IWIC_WRITE(sc, D_CMDR, cmd);
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}
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