623 lines
22 KiB
C
623 lines
22 KiB
C
/* $NetBSD: if_txpreg.h,v 1.6 2012/10/27 17:18:34 chs Exp $ */
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/*
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* Copyright (c) 2001 Aaron Campbell <aaron@monkey.org>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#define TXP_PCI_LOMEM 0x14 /* pci conf, memory map BAR */
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#define TXP_PCI_LOIO 0x10 /* pci conf, IO map BAR */
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/*
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* Typhoon registers.
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*/
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#define TXP_SRR 0x00 /* soft reset register */
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#define TXP_ISR 0x04 /* interrupt status register */
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#define TXP_IER 0x08 /* interrupt enable register */
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#define TXP_IMR 0x0c /* interrupt mask register */
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#define TXP_SIR 0x10 /* self interrupt register */
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#define TXP_H2A_7 0x14 /* host->arm comm 7 */
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#define TXP_H2A_6 0x18 /* host->arm comm 6 */
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#define TXP_H2A_5 0x1c /* host->arm comm 5 */
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#define TXP_H2A_4 0x20 /* host->arm comm 4 */
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#define TXP_H2A_3 0x24 /* host->arm comm 3 */
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#define TXP_H2A_2 0x28 /* host->arm comm 2 */
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#define TXP_H2A_1 0x2c /* host->arm comm 1 */
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#define TXP_H2A_0 0x30 /* host->arm comm 0 */
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#define TXP_A2H_3 0x34 /* arm->host comm 3 */
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#define TXP_A2H_2 0x38 /* arm->host comm 2 */
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#define TXP_A2H_1 0x3c /* arm->host comm 1 */
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#define TXP_A2H_0 0x40 /* arm->host comm 0 */
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/*
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* interrupt bits (IMR, ISR, IER)
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*/
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#define TXP_INT_RESERVED 0xffff0000
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#define TXP_INT_A2H_7 0x00008000 /* arm->host comm 7 */
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#define TXP_INT_A2H_6 0x00004000 /* arm->host comm 6 */
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#define TXP_INT_A2H_5 0x00002000 /* arm->host comm 5 */
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#define TXP_INT_A2H_4 0x00001000 /* arm->host comm 4 */
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#define TXP_INT_SELF 0x00000800 /* self interrupt */
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#define TXP_INT_PCI_TABORT 0x00000400 /* pci target abort */
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#define TXP_INT_PCI_MABORT 0x00000200 /* pci master abort */
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#define TXP_INT_DMA3 0x00000100 /* dma3 done */
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#define TXP_INT_DMA2 0x00000080 /* dma2 done */
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#define TXP_INT_DMA1 0x00000040 /* dma1 done */
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#define TXP_INT_DMA0 0x00000020 /* dma0 done */
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#define TXP_INT_A2H_3 0x00000010 /* arm->host comm 3 */
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#define TXP_INT_A2H_2 0x00000008 /* arm->host comm 2 */
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#define TXP_INT_A2H_1 0x00000004 /* arm->host comm 1 */
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#define TXP_INT_A2H_0 0x00000002 /* arm->host comm 0 */
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#define TXP_INT_LATCH 0x00000001 /* interrupt latch */
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/*
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* soft reset register (SRR)
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*/
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#define TXP_SRR_ALL 0x0000007f /* full reset */
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/*
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* Typhoon boot commands.
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*/
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#define TXP_BOOTCMD_NULL 0x00
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#define TXP_BOOTCMD_DOWNLOAD_COMPLETE 0xfb
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#define TXP_BOOTCMD_SEGMENT_AVAILABLE 0xfc
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#define TXP_BOOTCMD_RUNTIME_IMAGE 0xfd
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#define TXP_BOOTCMD_REGISTER_BOOT_RECORD 0xff
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/*
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* Typhoon runtime commands.
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*/
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#define TXP_CMD_GLOBAL_RESET 0x00
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#define TXP_CMD_TX_ENABLE 0x01
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#define TXP_CMD_TX_DISABLE 0x02
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#define TXP_CMD_RX_ENABLE 0x03
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#define TXP_CMD_RX_DISABLE 0x04
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#define TXP_CMD_RX_FILTER_WRITE 0x05
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#define TXP_CMD_RX_FILTER_READ 0x06
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#define TXP_CMD_READ_STATISTICS 0x07
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#define TXP_CMD_CYCLE_STATISTICS 0x08
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#define TXP_CMD_CLEAR_STATISTICS 0x09
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#define TXP_CMD_MEMORY_READ 0x0a
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#define TXP_CMD_MEMORY_WRITE_SINGLE 0x0b
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#define TXP_CMD_VARIABLE_SECTION_READ 0x0c
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#define TXP_CMD_VARIABLE_SECTION_WRITE 0x0d
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#define TXP_CMD_STATIC_SECTION_READ 0x0e
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#define TXP_CMD_STATIC_SECTION_WRITE 0x0f
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#define TXP_CMD_IMAGE_SECTION_PROGRAM 0x10
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#define TXP_CMD_NVRAM_PAGE_READ 0x11
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#define TXP_CMD_NVRAM_PAGE_WRITE 0x12
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#define TXP_CMD_XCVR_SELECT 0x13
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#define TXP_CMD_TEST_MUX 0x14
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#define TXP_CMD_PHYLOOPBACK_ENABLE 0x15
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#define TXP_CMD_PHYLOOPBACK_DISABLE 0x16
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#define TXP_CMD_MAC_CONTROL_READ 0x17
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#define TXP_CMD_MAC_CONTROL_WRITE 0x18
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#define TXP_CMD_MAX_PKT_SIZE_READ 0x19
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#define TXP_CMD_MAX_PKT_SIZE_WRITE 0x1a
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#define TXP_CMD_MEDIA_STATUS_READ 0x1b
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#define TXP_CMD_MEDIA_STATUS_WRITE 0x1c
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#define TXP_CMD_NETWORK_DIAGS_READ 0x1d
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#define TXP_CMD_NETWORK_DIAGS_WRITE 0x1e
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#define TXP_CMD_PHY_MGMT_READ 0x1f
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#define TXP_CMD_PHY_MGMT_WRITE 0x20
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#define TXP_CMD_VARIABLE_PARAMETER_READ 0x21
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#define TXP_CMD_VARIABLE_PARAMETER_WRITE 0x22
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#define TXP_CMD_GOTO_SLEEP 0x23
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#define TXP_CMD_FIREWALL_CONTROL 0x24
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#define TXP_CMD_MCAST_HASH_MASK_WRITE 0x25
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#define TXP_CMD_STATION_ADDRESS_WRITE 0x26
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#define TXP_CMD_STATION_ADDRESS_READ 0x27
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#define TXP_CMD_STATION_MASK_WRITE 0x28
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#define TXP_CMD_STATION_MASK_READ 0x29
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#define TXP_CMD_VLAN_ETHER_TYPE_READ 0x2a
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#define TXP_CMD_VLAN_ETHER_TYPE_WRITE 0x2b
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#define TXP_CMD_VLAN_MASK_READ 0x2c
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#define TXP_CMD_VLAN_MASK_WRITE 0x2d
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#define TXP_CMD_BCAST_THROTTLE_WRITE 0x2e
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#define TXP_CMD_BCAST_THROTTLE_READ 0x2f
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#define TXP_CMD_DHCP_PREVENT_WRITE 0x30
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#define TXP_CMD_DHCP_PREVENT_READ 0x31
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#define TXP_CMD_RECV_BUFFER_CONTROL 0x32
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#define TXP_CMD_SOFTWARE_RESET 0x33
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#define TXP_CMD_CREATE_SA 0x34
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#define TXP_CMD_DELETE_SA 0x35
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#define TXP_CMD_ENABLE_RX_IP_OPTION 0x36
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#define TXP_CMD_RANDOM_NUMBER_CONTROL 0x37
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#define TXP_CMD_RANDOM_NUMBER_READ 0x38
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#define TXP_CMD_MATRIX_TABLE_MODE_WRITE 0x39
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#define TXP_CMD_MATRIX_DETAIL_READ 0x3a
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#define TXP_CMD_FILTER_ARRAY_READ 0x3b
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#define TXP_CMD_FILTER_DETAIL_READ 0x3c
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#define TXP_CMD_FILTER_TABLE_MODE_WRITE 0x3d
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#define TXP_CMD_FILTER_TCL_WRITE 0x3e
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#define TXP_CMD_FILTER_TBL_READ 0x3f
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#define TXP_CMD_VERSIONS_READ 0x43
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#define TXP_CMD_FILTER_DEFINE 0x45
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#define TXP_CMD_ADD_WAKEUP_PKT 0x46
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#define TXP_CMD_ADD_SLEEP_PKT 0x47
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#define TXP_CMD_ENABLE_SLEEP_EVENTS 0x48
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#define TXP_CMD_ENABLE_WAKEUP_EVENTS 0x49
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#define TXP_CMD_GET_IP_ADDRESS 0x4a
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#define TXP_CMD_READ_PCI_REG 0x4c
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#define TXP_CMD_WRITE_PCI_REG 0x4d
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#define TXP_CMD_OFFLOAD_READ 0x4e
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#define TXP_CMD_OFFLOAD_WRITE 0x4f
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#define TXP_CMD_HELLO_RESPONSE 0x57
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#define TXP_CMD_ENABLE_RX_FILTER 0x58
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#define TXP_CMD_RX_FILTER_CAPABILITY 0x59
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#define TXP_CMD_HALT 0x5d
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#define TXP_CMD_READ_IPSEC_INFO 0x54
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#define TXP_CMD_GET_IPSEC_ENABLE 0x67
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#define TXP_CMD_INVALID 0xffff
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#define TXP_FRAGMENT 0x0000
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#define TXP_TXFRAME 0x0001
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#define TXP_COMMAND 0x0002
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#define TXP_OPTION 0x0003
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#define TXP_RECEIVE 0x0004
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#define TXP_RESPONSE 0x0005
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#define TXP_TYPE_IPSEC 0x0000
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#define TXP_TYPE_TCPSEGMENT 0x0001
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#define TXP_PFLAG_NOCRC 0x0000
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#define TXP_PFLAG_IPCKSUM 0x0001
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#define TXP_PFLAG_TCPCKSUM 0x0002
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#define TXP_PFLAG_TCPSEGMENT 0x0004
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#define TXP_PFLAG_INSERTVLAN 0x0008
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#define TXP_PFLAG_IPSEC 0x0010
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#define TXP_PFLAG_PRIORITY 0x0020
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#define TXP_PFLAG_UDPCKSUM 0x0040
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#define TXP_PFLAG_PADFRAME 0x0080
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#define TXP_MISC_FIRSTDESC 0x0000
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#define TXP_MISC_LASTDESC 0x0001
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#define TXP_ERR_INTERNAL 0x0000
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#define TXP_ERR_FIFOUNDERRUN 0x0001
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#define TXP_ERR_BADSSD 0x0002
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#define TXP_ERR_RUNT 0x0003
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#define TXP_ERR_CRC 0x0004
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#define TXP_ERR_OVERSIZE 0x0005
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#define TXP_ERR_ALIGNMENT 0x0006
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#define TXP_ERR_DRIBBLEBIT 0x0007
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#define TXP_PROTO_UNKNOWN 0x0000
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#define TXP_PROTO_IP 0x0001
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#define TXP_PROTO_IPX 0x0002
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#define TXP_PROTO_RESERVED 0x0003
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#define TXP_STAT_PROTO 0x0001
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#define TXP_STAT_VLAN 0x0002
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#define TXP_STAT_IPFRAGMENT 0x0004
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#define TXP_STAT_IPSEC 0x0008
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#define TXP_STAT_IPCKSUMBAD 0x0010
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#define TXP_STAT_TCPCKSUMBAD 0x0020
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#define TXP_STAT_UDPCKSUMBAD 0x0040
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#define TXP_STAT_IPCKSUMGOOD 0x0080
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#define TXP_STAT_TCPCKSUMGOOD 0x0100
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#define TXP_STAT_UDPCKSUMGOOD 0x0200
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struct txp_tx_desc {
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volatile u_int8_t tx_flags; /* type/descriptor flags */
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volatile u_int8_t tx_numdesc; /* number of descriptors */
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volatile u_int16_t tx_totlen; /* total packet length */
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volatile u_int32_t tx_addrlo; /* virt addr low word */
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volatile u_int32_t tx_addrhi; /* virt addr high word */
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volatile u_int32_t tx_pflags; /* processing flags */
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};
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#define TX_FLAGS_TYPE_M 0x07 /* type mask */
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#define TX_FLAGS_TYPE_FRAG 0x00 /* type: fragment */
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#define TX_FLAGS_TYPE_DATA 0x01 /* type: data frame */
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#define TX_FLAGS_TYPE_CMD 0x02 /* type: command frame */
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#define TX_FLAGS_TYPE_OPT 0x03 /* type: options */
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#define TX_FLAGS_TYPE_RX 0x04 /* type: command */
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#define TX_FLAGS_TYPE_RESP 0x05 /* type: response */
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#define TX_FLAGS_RESP 0x40 /* response requested */
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#define TX_FLAGS_VALID 0x80 /* valid descriptor */
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#define TX_PFLAGS_DNAC 0x00000001 /* do not add crc */
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#define TX_PFLAGS_IPCKSUM 0x00000002 /* ip checksum */
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#define TX_PFLAGS_TCPCKSUM 0x00000004 /* tcp checksum */
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#define TX_PFLAGS_TCPSEG 0x00000008 /* tcp segmentation */
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#define TX_PFLAGS_VLAN 0x00000010 /* insert vlan */
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#define TX_PFLAGS_IPSEC 0x00000020 /* perform ipsec */
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#define TX_PFLAGS_PRIO 0x00000040 /* priority field valid */
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#define TX_PFLAGS_UDPCKSUM 0x00000080 /* udp checksum */
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#define TX_PFLAGS_PADFRAME 0x00000100 /* pad frame */
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#define TX_PFLAGS_VLANTAG_M 0x0ffff000 /* vlan tag mask */
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#define TX_PFLAGS_VLANPRI_M 0x00700000 /* vlan priority mask */
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#define TX_PFLAGS_VLANTAG_S 12 /* amount to shift tag */
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struct txp_rx_desc {
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volatile u_int8_t rx_flags; /* type/descriptor flags */
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volatile u_int8_t rx_numdesc; /* number of descriptors */
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volatile u_int16_t rx_len; /* frame length */
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volatile u_int32_t rx_vaddrlo; /* virtual address, lo word */
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volatile u_int32_t rx_vaddrhi; /* virtual address, hi word */
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volatile u_int32_t rx_stat; /* status */
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volatile u_int16_t rx_filter; /* filter status */
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volatile u_int16_t rx_hash; /* hash status */
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volatile u_int32_t rx_vlan; /* vlan tag/priority */
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};
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/* txp_rx_desc.rx_flags */
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#define RX_FLAGS_TYPE_M 0x07 /* type mask */
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#define RX_FLAGS_TYPE_FRAG 0x00 /* type: fragment */
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#define RX_FLAGS_TYPE_DATA 0x01 /* type: data frame */
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#define RX_FLAGS_TYPE_CMD 0x02 /* type: command frame */
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#define RX_FLAGS_TYPE_OPT 0x03 /* type: options */
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#define RX_FLAGS_TYPE_RX 0x04 /* type: command */
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#define RX_FLAGS_TYPE_RESP 0x05 /* type: response */
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#define RX_FLAGS_RCV_TYPE_M 0x18 /* rcvtype mask */
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#define RX_FLAGS_RCV_TYPE_RX 0x00 /* rcvtype: receive */
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#define RX_FLAGS_RCV_TYPE_RSP 0x08 /* rcvtype: response */
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#define RX_FLAGS_ERROR 0x40 /* error in packet */
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/* txp_rx_desc.rx_stat (if rx_flags & RX_FLAGS_ERROR bit set) */
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#define RX_ERROR_ADAPTER 0x00000000 /* adapter internal error */
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#define RX_ERROR_FIFO 0x00000001 /* fifo underrun */
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#define RX_ERROR_BADSSD 0x00000002 /* bad ssd */
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#define RX_ERROR_RUNT 0x00000003 /* runt packet */
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#define RX_ERROR_CRC 0x00000004 /* bad crc */
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#define RX_ERROR_OVERSIZE 0x00000005 /* oversized packet */
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#define RX_ERROR_ALIGN 0x00000006 /* alignment error */
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#define RX_ERROR_DRIBBLE 0x00000007 /* dribble bit */
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/* txp_rx_desc.rx_stat (if rx_flags & RX_FLAGS_ERROR not bit set) */
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#define RX_STAT_PROTO_M 0x00000003 /* protocol mask */
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#define RX_STAT_PROTO_UK 0x00000000 /* unknown protocol */
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#define RX_STAT_PROTO_IPX 0x00000001 /* IPX */
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#define RX_STAT_PROTO_IP 0x00000002 /* IP */
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#define RX_STAT_PROTO_RSV 0x00000003 /* reserved */
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#define RX_STAT_VLAN 0x00000004 /* vlan tag (in rxd) */
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#define RX_STAT_IPFRAG 0x00000008 /* fragment, ipsec not done */
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#define RX_STAT_IPSEC 0x00000010 /* ipsec decoded packet */
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#define RX_STAT_IPCKSUMBAD 0x00000020 /* ip checksum failed */
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#define RX_STAT_UDPCKSUMBAD 0x00000040 /* udp checksum failed */
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#define RX_STAT_TCPCKSUMBAD 0x00000080 /* tcp checksum failed */
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#define RX_STAT_IPCKSUMGOOD 0x00000100 /* ip checksum succeeded */
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#define RX_STAT_UDPCKSUMGOOD 0x00000200 /* udp checksum succeeded */
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#define RX_STAT_TCPCKSUMGOOD 0x00000400 /* tcp checksum succeeded */
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struct txp_rxbuf_desc {
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volatile u_int32_t rb_paddrlo;
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volatile u_int32_t rb_paddrhi;
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volatile u_int32_t rb_vaddrlo;
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volatile u_int32_t rb_vaddrhi;
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};
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/* Extension descriptor */
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struct txp_ext_desc {
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volatile u_int32_t ext_1;
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volatile u_int32_t ext_2;
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volatile u_int32_t ext_3;
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volatile u_int32_t ext_4;
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};
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struct txp_cmd_desc {
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volatile u_int8_t cmd_flags;
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volatile u_int8_t cmd_numdesc;
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volatile u_int16_t cmd_id;
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volatile u_int16_t cmd_seq;
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volatile u_int16_t cmd_par1;
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volatile u_int32_t cmd_par2;
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volatile u_int32_t cmd_par3;
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};
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#define CMD_FLAGS_TYPE_M 0x07 /* type mask */
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#define CMD_FLAGS_TYPE_FRAG 0x00 /* type: fragment */
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#define CMD_FLAGS_TYPE_DATA 0x01 /* type: data frame */
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#define CMD_FLAGS_TYPE_CMD 0x02 /* type: command frame */
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#define CMD_FLAGS_TYPE_OPT 0x03 /* type: options */
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#define CMD_FLAGS_TYPE_RX 0x04 /* type: command */
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#define CMD_FLAGS_TYPE_RESP 0x05 /* type: response */
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#define CMD_FLAGS_RESP 0x40 /* response requested */
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#define CMD_FLAGS_VALID 0x80 /* valid descriptor */
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struct txp_rsp_desc {
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volatile u_int8_t rsp_flags;
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volatile u_int8_t rsp_numdesc;
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volatile u_int16_t rsp_id;
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volatile u_int16_t rsp_seq;
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volatile u_int16_t rsp_par1;
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volatile u_int32_t rsp_par2;
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volatile u_int32_t rsp_par3;
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};
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#define RSP_FLAGS_TYPE_M 0x07 /* type mask */
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#define RSP_FLAGS_TYPE_FRAG 0x00 /* type: fragment */
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#define RSP_FLAGS_TYPE_DATA 0x01 /* type: data frame */
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#define RSP_FLAGS_TYPE_CMD 0x02 /* type: command frame */
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#define RSP_FLAGS_TYPE_OPT 0x03 /* type: options */
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#define RSP_FLAGS_TYPE_RX 0x04 /* type: command */
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#define RSP_FLAGS_TYPE_RESP 0x05 /* type: response */
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#define RSP_FLAGS_ERROR 0x40 /* response error */
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struct txp_frag_desc {
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volatile u_int8_t frag_flags; /* type/descriptor flags */
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volatile u_int8_t frag_rsvd1;
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volatile u_int16_t frag_len; /* bytes in this fragment */
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volatile u_int32_t frag_addrlo; /* phys addr low word */
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volatile u_int32_t frag_addrhi; /* phys addr high word */
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volatile u_int32_t frag_rsvd2;
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};
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#define FRAG_FLAGS_TYPE_M 0x07 /* type mask */
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#define FRAG_FLAGS_TYPE_FRAG 0x00 /* type: fragment */
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#define FRAG_FLAGS_TYPE_DATA 0x01 /* type: data frame */
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#define FRAG_FLAGS_TYPE_CMD 0x02 /* type: command frame */
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#define FRAG_FLAGS_TYPE_OPT 0x03 /* type: options */
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#define FRAG_FLAGS_TYPE_RX 0x04 /* type: command */
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#define FRAG_FLAGS_TYPE_RESP 0x05 /* type: response */
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#define FRAG_FLAGS_VALID 0x80 /* valid descriptor */
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|
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struct txp_opt_desc {
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|
u_int8_t opt_desctype:3,
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opt_rsvd:1,
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opt_type:4;
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|
u_int8_t opt_num;
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u_int16_t opt_dep1;
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u_int32_t opt_dep2;
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u_int32_t opt_dep3;
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u_int32_t opt_dep4;
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|
};
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|
|
struct txp_ipsec_desc {
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u_int8_t ipsec_desctpe:3,
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ipsec_rsvd:1,
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ipsec_type:4;
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u_int8_t ipsec_num;
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u_int16_t ipsec_flags;
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u_int16_t ipsec_ah1;
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u_int16_t ipsec_esp1;
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u_int16_t ipsec_ah2;
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u_int16_t ipsec_esp2;
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u_int32_t ipsec_rsvd1;
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};
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struct txp_tcpseg_desc {
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u_int8_t tcpseg_desctype:3,
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tcpseg_rsvd:1,
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tcpseg_type:4;
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u_int8_t tcpseg_num;
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u_int16_t tcpseg_mss:12,
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tcpseg_misc:4;
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u_int32_t tcpseg_respaddr;
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u_int32_t tcpseg_txbytes;
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u_int32_t tcpseg_lss;
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};
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|
|
/*
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* Transceiver types
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*/
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|
#define TXP_XCVR_10_HDX 0
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#define TXP_XCVR_10_FDX 1
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#define TXP_XCVR_100_HDX 2
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#define TXP_XCVR_100_FDX 3
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#define TXP_XCVR_AUTO 4
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#define TXP_MEDIA_CRC 0x0004 /* crc strip disable */
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#define TXP_MEDIA_CD 0x0010 /* collision detection */
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#define TXP_MEDIA_CS 0x0020 /* carrier sense */
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#define TXP_MEDIA_POL 0x0400 /* polarity reversed */
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#define TXP_MEDIA_NOLINK 0x0800 /* 0 = link, 1 = no link */
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|
|
/*
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* receive filter bits (par1 to TXP_CMD_RX_FILTER_{READ|WRITE}
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|
*/
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#define TXP_RXFILT_DIRECT 0x0001 /* directed packets */
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#define TXP_RXFILT_ALLMULTI 0x0002 /* all multicast packets */
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#define TXP_RXFILT_BROADCAST 0x0004 /* broadcast packets */
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#define TXP_RXFILT_PROMISC 0x0008 /* promiscuous mode */
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#define TXP_RXFILT_HASHMULTI 0x0010 /* use multicast filter */
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|
|
|
/* multicast polynomial */
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|
#define TXP_POLYNOMIAL 0x04c11db7
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|
|
/*
|
|
* boot record (pointers to rings)
|
|
*/
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struct txp_boot_record {
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volatile u_int32_t br_hostvar_lo; /* host ring pointer */
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volatile u_int32_t br_hostvar_hi;
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volatile u_int32_t br_txlopri_lo; /* tx low pri ring */
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volatile u_int32_t br_txlopri_hi;
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|
volatile u_int32_t br_txlopri_siz;
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|
volatile u_int32_t br_txhipri_lo; /* tx high pri ring */
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|
volatile u_int32_t br_txhipri_hi;
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volatile u_int32_t br_txhipri_siz;
|
|
volatile u_int32_t br_rxlopri_lo; /* rx low pri ring */
|
|
volatile u_int32_t br_rxlopri_hi;
|
|
volatile u_int32_t br_rxlopri_siz;
|
|
volatile u_int32_t br_rxbuf_lo; /* rx buffer ring */
|
|
volatile u_int32_t br_rxbuf_hi;
|
|
volatile u_int32_t br_rxbuf_siz;
|
|
volatile u_int32_t br_cmd_lo; /* command ring */
|
|
volatile u_int32_t br_cmd_hi;
|
|
volatile u_int32_t br_cmd_siz;
|
|
volatile u_int32_t br_resp_lo; /* response ring */
|
|
volatile u_int32_t br_resp_hi;
|
|
volatile u_int32_t br_resp_siz;
|
|
volatile u_int32_t br_zero_lo; /* zero word */
|
|
volatile u_int32_t br_zero_hi;
|
|
volatile u_int32_t br_rxhipri_lo; /* rx high pri ring */
|
|
volatile u_int32_t br_rxhipri_hi;
|
|
volatile u_int32_t br_rxhipri_siz;
|
|
};
|
|
|
|
/*
|
|
* hostvar structure (shared with typhoon)
|
|
*/
|
|
struct txp_hostvar {
|
|
volatile u_int32_t hv_rx_hi_read_idx; /* host->arm */
|
|
volatile u_int32_t hv_rx_lo_read_idx; /* host->arm */
|
|
volatile u_int32_t hv_rx_buf_write_idx; /* host->arm */
|
|
volatile u_int32_t hv_resp_read_idx; /* host->arm */
|
|
volatile u_int32_t hv_tx_lo_desc_read_idx; /* arm->host */
|
|
volatile u_int32_t hv_tx_hi_desc_read_idx; /* arm->host */
|
|
volatile u_int32_t hv_rx_lo_write_idx; /* arm->host */
|
|
volatile u_int32_t hv_rx_buf_read_idx; /* arm->host */
|
|
volatile u_int32_t hv_cmd_read_idx; /* arm->host */
|
|
volatile u_int32_t hv_resp_write_idx; /* arm->host */
|
|
volatile u_int32_t hv_rx_hi_write_idx; /* arm->host */
|
|
};
|
|
|
|
/*
|
|
* TYPHOON status register state (in TXP_A2H_0)
|
|
*/
|
|
#define STAT_ROM_CODE 0x00000001
|
|
#define STAT_ROM_EEPROM_LOAD 0x00000002
|
|
#define STAT_WAITING_FOR_BOOT 0x00000007
|
|
#define STAT_RUNNING 0x00000009
|
|
#define STAT_WAITING_FOR_HOST_REQUEST 0x0000000d
|
|
#define STAT_WAITING_FOR_SEGMENT 0x00000010
|
|
#define STAT_SLEEPING 0x00000011
|
|
#define STAT_HALTED 0x00000014
|
|
|
|
#define TX_ENTRIES 256
|
|
#define RX_ENTRIES 128
|
|
#define RXBUF_ENTRIES 256
|
|
#define CMD_ENTRIES 32
|
|
#define RSP_ENTRIES 32
|
|
|
|
#define OFFLOAD_TCPCKSUM 0x00000002 /* tcp checksum */
|
|
#define OFFLOAD_UDPCKSUM 0x00000004 /* udp checksum */
|
|
#define OFFLOAD_IPCKSUM 0x00000008 /* ip checksum */
|
|
#define OFFLOAD_IPSEC 0x00000010 /* ipsec enable */
|
|
#define OFFLOAD_BCAST 0x00000020 /* broadcast throttle */
|
|
#define OFFLOAD_DHCP 0x00000040 /* dhcp prevention */
|
|
#define OFFLOAD_VLAN 0x00000080 /* vlan enable */
|
|
#define OFFLOAD_FILTER 0x00000100 /* filter enable */
|
|
#define OFFLOAD_TCPSEG 0x00000200 /* tcp segmentation */
|
|
#define OFFLOAD_MASK 0xfffffffe /* mask off low bit */
|
|
|
|
/*
|
|
* Macros for converting array indices to offsets within the descriptor
|
|
* arrays. The chip operates on offsets, but it's much easier for us
|
|
* to operate on indices. Assumes descriptor entries are 16 bytes.
|
|
*/
|
|
#define TXP_IDX2OFFSET(idx) ((idx) << 4)
|
|
#define TXP_OFFSET2IDX(off) ((off) >> 4)
|
|
|
|
struct txp_dma_alloc {
|
|
u_int64_t dma_paddr;
|
|
void * dma_vaddr;
|
|
bus_dmamap_t dma_map;
|
|
bus_dma_segment_t dma_seg;
|
|
int dma_nseg;
|
|
};
|
|
|
|
struct txp_cmd_ring {
|
|
struct txp_cmd_desc *base;
|
|
u_int32_t lastwrite;
|
|
u_int32_t size;
|
|
};
|
|
|
|
struct txp_rsp_ring {
|
|
struct txp_rsp_desc *base;
|
|
u_int32_t lastwrite;
|
|
u_int32_t size;
|
|
};
|
|
|
|
struct txp_tx_ring {
|
|
struct txp_tx_desc *r_desc; /* base address of descs */
|
|
u_int32_t r_reg; /* register to activate */
|
|
u_int32_t r_prod; /* producer */
|
|
u_int32_t r_cons; /* consumer */
|
|
u_int32_t r_cnt; /* # descs in use */
|
|
volatile u_int32_t *r_off; /* hostvar index pointer */
|
|
};
|
|
|
|
struct txp_swdesc {
|
|
struct mbuf * sd_mbuf;
|
|
bus_dmamap_t sd_map;
|
|
};
|
|
|
|
struct txp_rx_ring {
|
|
struct txp_rx_desc *r_desc; /* base address of descs */
|
|
volatile u_int32_t *r_roff; /* hv read offset ptr */
|
|
volatile u_int32_t *r_woff; /* hv write offset ptr */
|
|
};
|
|
|
|
struct txp_softc {
|
|
device_t sc_dev; /* base device */
|
|
struct ethercom sc_arpcom; /* ethernet common */
|
|
struct txp_hostvar *sc_hostvar;
|
|
struct txp_boot_record *sc_boot;
|
|
bus_space_handle_t sc_bh; /* bus handle (regs) */
|
|
bus_space_tag_t sc_bt; /* bus tag (regs) */
|
|
bus_dma_tag_t sc_dmat; /* dma tag */
|
|
struct txp_cmd_ring sc_cmdring;
|
|
struct txp_rsp_ring sc_rspring;
|
|
struct txp_swdesc sc_txd[TX_ENTRIES];
|
|
void * sc_ih;
|
|
struct callout sc_tick;
|
|
struct ifmedia sc_ifmedia;
|
|
struct txp_tx_ring sc_txhir, sc_txlor;
|
|
struct txp_rxbuf_desc *sc_rxbufs;
|
|
struct txp_rx_ring sc_rxhir, sc_rxlor;
|
|
u_int16_t sc_xcvr;
|
|
u_int16_t sc_seq;
|
|
struct txp_dma_alloc sc_boot_dma, sc_host_dma, sc_zero_dma;
|
|
struct txp_dma_alloc sc_rxhiring_dma, sc_rxloring_dma;
|
|
struct txp_dma_alloc sc_txhiring_dma, sc_txloring_dma;
|
|
struct txp_dma_alloc sc_cmdring_dma, sc_rspring_dma;
|
|
struct txp_dma_alloc sc_rxbufring_dma;
|
|
int sc_cold;
|
|
u_int32_t sc_rx_capability, sc_tx_capability;
|
|
int sc_flags;
|
|
#define TXP_USESUBSYSTEM 0x1 /* use PCI subsys reg for detail info */
|
|
#define TXP_SERVERVERSION 0x2
|
|
#define TXP_FIBER 0x4
|
|
};
|
|
|
|
#define TXP_DEVNAME(sc) ((sc)->sc_cold ? "" : device_xname((sc)->sc_dev))
|
|
|
|
struct txp_fw_file_header {
|
|
u_int8_t magicid[8]; /* TYPHOON\0 */
|
|
u_int32_t version;
|
|
u_int32_t nsections;
|
|
u_int32_t addr;
|
|
};
|
|
|
|
struct txp_fw_section_header {
|
|
u_int32_t nbytes;
|
|
u_int16_t cksum;
|
|
u_int16_t reserved;
|
|
u_int32_t addr;
|
|
};
|
|
|
|
#define TXP_MAX_SEGLEN 0xffff
|
|
#define TXP_MAX_PKTLEN 0x0800
|
|
|
|
#define WRITE_REG(sc,reg,val) \
|
|
bus_space_write_4((sc)->sc_bt, (sc)->sc_bh, reg, val)
|
|
#define READ_REG(sc,reg) \
|
|
bus_space_read_4((sc)->sc_bt, (sc)->sc_bh, reg)
|
|
|