296 lines
10 KiB
C
296 lines
10 KiB
C
/* $NetBSD: if_bgevar.h,v 1.9 2012/02/02 19:43:05 tls Exp $ */
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/*
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* Copyright (c) 2001 Wind River Systems
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* Copyright (c) 1997, 1998, 1999, 2001
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* Bill Paul <wpaul@windriver.com>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD: if_bgereg.h,v 1.1.2.7 2002/11/02 18:17:55 mp Exp $
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*/
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/*
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* BCM570x memory map. The internal memory layout varies somewhat
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* depending on whether or not we have external SSRAM attached.
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* The BCM5700 can have up to 16MB of external memory. The BCM5701
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* is apparently not designed to use external SSRAM. The mappings
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* up to the first 4 send rings are the same for both internal and
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* external memory configurations. Note that mini RX ring space is
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* only available with external SSRAM configurations, which means
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* the mini RX ring is not supported on the BCM5701.
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*
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* The NIC's memory can be accessed by the host in one of 3 ways:
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*
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* 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA
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* registers in PCI config space can be used to read any 32-bit
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* address within the NIC's memory.
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*
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* 2) Memory window access. The MEMWIN_BASEADDR register in PCI config
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* space can be used in conjunction with the memory window in the
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* device register space at offset 0x8000 to read any 32K chunk
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* of NIC memory.
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*
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* 3) Flat mode. If the 'flat mode' bit in the PCI state register is
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* set, the device I/O mapping consumes 32MB of host address space,
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* allowing all of the registers and internal NIC memory to be
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* accessed directly. NIC memory addresses are offset by 0x01000000.
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* Flat mode consumes so much host address space that it is not
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* recommended.
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*/
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#ifndef _DEV_PCI_IF_BGEVAR_H_
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#define _DEV_PCI_IF_BGEVAR_H_
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#include <sys/bus.h>
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#include <net/if_ether.h>
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#include <dev/pci/pcivar.h>
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#define BGE_HOSTADDR(x, y) \
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do { \
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(x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \
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if (sizeof (bus_addr_t) == 8) \
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(x).bge_addr_hi = ((uint64_t) (y) >> 32); \
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else \
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(x).bge_addr_hi = 0; \
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} while(0)
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#define RCB_WRITE_4(sc, rcb, offset, val) \
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bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \
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rcb + offsetof(struct bge_rcb, offset), val)
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/*
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* Other utility macros.
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*/
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#define BGE_INC(x, y) (x) = (x + 1) % y
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/*
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* Register access macros. The Tigon always uses memory mapped register
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* accesses and all registers must be accessed with 32 bit operations.
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*/
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#define CSR_WRITE_4(sc, reg, val) \
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bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val)
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#define CSR_READ_4(sc, reg) \
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bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg)
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#define BGE_SETBIT(sc, reg, x) \
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CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x))
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#define BGE_CLRBIT(sc, reg, x) \
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CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x))
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#define PCI_SETBIT(pc, tag, reg, x) \
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pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | x))
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#define PCI_CLRBIT(pc, tag, reg, x) \
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pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~x))
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/*
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* Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS
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* values are tuneable. They control the actual amount of buffers
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* allocated for the standard, mini and jumbo receive rings.
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*/
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#define BGE_SSLOTS 256
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#define BGE_MSLOTS 256
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#define BGE_JSLOTS 384
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#define BGE_RSLOTS 256
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#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN)
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#define BGE_JLEN (BGE_JRAWLEN + (sizeof(uint64_t) - \
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(BGE_JRAWLEN % sizeof(uint64_t))))
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#define BGE_JPAGESZ PAGE_SIZE
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#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ)
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#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID)
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/*
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* Ring structures. Most of these reside in host memory and we tell
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* the NIC where they are via the ring control blocks. The exceptions
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* are the tx and command rings, which live in NIC memory and which
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* we access via the shared memory window.
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*/
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struct bge_ring_data {
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struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT];
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struct bge_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT];
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struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT];
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struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT];
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struct bge_status_block bge_status_block;
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struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */
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struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */
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struct bge_gib bge_info;
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};
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#define BGE_RING_DMA_ADDR(sc, offset) \
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((sc)->bge_ring_map->dm_segs[0].ds_addr + \
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offsetof(struct bge_ring_data, offset))
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/*
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* Number of DMA segments in a TxCB. Note that this is carefully
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* chosen to make the total struct size an even power of two. It's
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* critical that no TxCB be split across a page boundary since
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* no attempt is made to allocate physically contiguous memory.
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*
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*/
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#if 0 /* pre-TSO values */
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#define BGE_TXDMA_MAX ETHER_MAX_LEN_JUMBO
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#ifdef _LP64
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#define BGE_NTXSEG 30
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#else
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#define BGE_NTXSEG 31
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#endif
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#else /* TSO values */
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#define BGE_TXDMA_MAX (round_page(IP_MAXPACKET)) /* for TSO */
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#ifdef _LP64
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#define BGE_NTXSEG 120 /* XXX just a guess */
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#else
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#define BGE_NTXSEG 124 /* XXX just a guess */
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#endif
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#endif /* TSO values */
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/*
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* Mbuf pointers. We need these to keep track of the virtual addresses
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* of our mbuf chains since we can only convert from physical to virtual,
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* not the other way around.
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*/
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struct bge_chain_data {
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struct mbuf *bge_tx_chain[BGE_TX_RING_CNT];
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struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT];
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struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT];
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struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT];
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bus_dmamap_t bge_rx_std_map[BGE_STD_RX_RING_CNT];
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bus_dmamap_t bge_rx_jumbo_map;
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/* Stick the jumbo mem management stuff here too. */
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void * bge_jslots[BGE_JSLOTS];
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void * bge_jumbo_buf;
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};
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#define BGE_JUMBO_DMA_ADDR(sc, m) \
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((sc)->bge_cdata.bge_rx_jumbo_map->dm_segs[0].ds_addr + \
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(mtod((m), char *) - (char *)(sc)->bge_cdata.bge_jumbo_buf))
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struct bge_type {
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uint16_t bge_vid;
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uint16_t bge_did;
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char *bge_name;
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};
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#define BGE_TIMEOUT 100000
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#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */
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struct bge_jpool_entry {
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int slot;
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SLIST_ENTRY(bge_jpool_entry) jpool_entries;
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};
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struct bge_bcom_hack {
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int reg;
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int val;
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};
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struct txdmamap_pool_entry {
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bus_dmamap_t dmamap;
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SLIST_ENTRY(txdmamap_pool_entry) link;
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};
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#define ASF_ENABLE 1
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#define ASF_NEW_HANDSHAKE 2
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#define ASF_STACKUP 4
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struct bge_softc {
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device_t bge_dev;
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struct ethercom ethercom; /* interface info */
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bus_space_handle_t bge_bhandle;
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bus_space_tag_t bge_btag;
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void *bge_intrhand;
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pci_chipset_tag_t sc_pc;
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pcitag_t sc_pcitag;
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struct mii_data bge_mii;
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struct ifmedia bge_ifmedia; /* media info */
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uint32_t bge_return_ring_cnt;
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uint32_t bge_tx_prodidx;
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bus_dma_tag_t bge_dmatag;
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uint32_t bge_pcixcap;
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uint32_t bge_pciecap;
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uint32_t bge_chipid;
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uint32_t bge_local_ctrl_reg;
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uint8_t bge_asf_mode;
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uint8_t bge_asf_count;
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struct bge_ring_data *bge_rdata; /* rings */
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struct bge_chain_data bge_cdata; /* mbufs */
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bus_dmamap_t bge_ring_map;
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uint16_t bge_tx_saved_considx;
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uint16_t bge_rx_saved_considx;
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uint16_t bge_ev_saved_considx;
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uint16_t bge_std; /* current std ring head */
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uint16_t bge_jumbo; /* current jumo ring head */
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SLIST_HEAD(__bge_jfreehead, bge_jpool_entry) bge_jfree_listhead;
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SLIST_HEAD(__bge_jinusehead, bge_jpool_entry) bge_jinuse_listhead;
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uint32_t bge_stat_ticks;
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uint32_t bge_rx_coal_ticks;
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uint32_t bge_tx_coal_ticks;
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uint32_t bge_rx_max_coal_bds;
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uint32_t bge_tx_max_coal_bds;
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uint32_t bge_tx_buf_ratio;
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uint32_t bge_sts;
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#define BGE_STS_LINK 0x00000001 /* MAC link status */
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#define BGE_STS_LINK_EVT 0x00000002 /* pending link event */
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#define BGE_STS_AUTOPOLL 0x00000004 /* PHY auto-polling */
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#define BGE_STS_BIT(sc, x) ((sc)->bge_sts & (x))
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#define BGE_STS_SETBIT(sc, x) ((sc)->bge_sts |= (x))
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#define BGE_STS_CLRBIT(sc, x) ((sc)->bge_sts &= ~(x))
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int bge_if_flags;
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uint32_t bge_flags;
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int bge_flowflags;
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#ifdef BGE_EVENT_COUNTERS
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/*
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* Event counters.
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*/
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struct evcnt bge_ev_intr; /* interrupts */
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struct evcnt bge_ev_tx_xoff; /* send PAUSE(len>0) packets */
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struct evcnt bge_ev_tx_xon; /* send PAUSE(len=0) packets */
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struct evcnt bge_ev_rx_xoff; /* receive PAUSE(len>0) packets */
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struct evcnt bge_ev_rx_xon; /* receive PAUSE(len=0) packets */
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struct evcnt bge_ev_rx_macctl; /* receive MAC control packets */
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struct evcnt bge_ev_xoffentered;/* XOFF state entered */
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#endif /* BGE_EVENT_COUNTERS */
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int bge_txcnt;
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struct callout bge_timeout;
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char *bge_vpd_prodname;
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char *bge_vpd_readonly;
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int bge_pending_rxintr_change;
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SLIST_HEAD(, txdmamap_pool_entry) txdma_list;
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struct txdmamap_pool_entry *txdma[BGE_TX_RING_CNT];
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struct sysctllog *bge_log;
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krndsource_t rnd_source; /* random source */
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};
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#endif /* _DEV_PCI_IF_BGEVAR_H_ */
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