143 lines
4.0 KiB
C
143 lines
4.0 KiB
C
/* $NetBSD: dpt_pci.c,v 1.26 2012/10/27 17:18:31 chs Exp $ */
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/*
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* Copyright (c) 1999, 2000, 2001 Andrew Doran <ad@NetBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* PCI front-end for DPT EATA SCSI driver.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: dpt_pci.c,v 1.26 2012/10/27 17:18:31 chs Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/queue.h>
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#include <sys/bus.h>
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#include <sys/intr.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pcivar.h>
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#include <dev/ic/dptreg.h>
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#include <dev/ic/dptvar.h>
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#include <dev/i2o/dptivar.h>
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#define PCI_CBMA 0x14 /* Configuration base memory address */
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#define PCI_CBIO 0x10 /* Configuration base I/O address */
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static int dpt_pci_match(device_t, cfdata_t, void *);
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static void dpt_pci_attach(device_t, device_t, void *);
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CFATTACH_DECL_NEW(dpt_pci, sizeof(struct dpt_softc),
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dpt_pci_match, dpt_pci_attach, NULL, NULL);
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static int
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dpt_pci_match(device_t parent, cfdata_t match, void *aux)
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{
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struct pci_attach_args *pa;
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pa = (struct pci_attach_args *)aux;
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_DPT &&
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PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_DPT_SC_RAID)
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return (1);
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return (0);
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}
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static void
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dpt_pci_attach(device_t parent, device_t self, void *aux)
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{
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struct pci_attach_args *pa;
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struct dpt_softc *sc;
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pci_chipset_tag_t pc;
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pci_intr_handle_t ih;
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bus_space_handle_t ioh;
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const char *intrstr;
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pcireg_t csr;
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aprint_naive(": Storage controller\n");
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sc = device_private(self);
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sc->sc_dev = self;
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pa = (struct pci_attach_args *)aux;
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pc = pa->pa_pc;
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aprint_normal(": ");
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if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, &sc->sc_iot,
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&ioh, NULL, NULL)) {
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aprint_error("can't map i/o space\n");
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return;
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}
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/* Need to map in by 16 registers. */
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if (bus_space_subregion(sc->sc_iot, ioh, 16, 16, &sc->sc_ioh)) {
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aprint_error("can't map i/o subregion\n");
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return;
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}
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sc->sc_dmat = pa->pa_dmat;
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/* Enable the device. */
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csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
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pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
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csr | PCI_COMMAND_MASTER_ENABLE);
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/* Map and establish the interrupt. */
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if (pci_intr_map(pa, &ih)) {
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aprint_error("can't map interrupt\n");
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return;
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}
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intrstr = pci_intr_string(pc, ih);
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sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, dpt_intr, sc);
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if (sc->sc_ih == NULL) {
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aprint_error("can't establish interrupt");
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if (intrstr != NULL)
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aprint_error(" at %s", intrstr);
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aprint_error("\n");
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return;
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}
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/* Read the EATA configuration. */
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if (dpt_readcfg(sc)) {
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aprint_error_dev(sc->sc_dev, "readcfg failed - see dpt(4)\n");
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return;
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}
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sc->sc_bustype = SI_PCI_BUS;
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/* Now attach to the bus-independent code. */
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dpt_init(sc, intrstr);
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}
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