206 lines
7.0 KiB
C
206 lines
7.0 KiB
C
/* $NetBSD: cpu.h,v 1.22 1997/06/22 07:42:48 jonathan Exp $ */
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/*-
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Ralph Campbell and Rick Macklem.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)cpu.h 8.4 (Berkeley) 1/4/94
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*/
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#ifndef _CPU_H_
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#define _CPU_H_
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/*
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* Exported definitions unique to NetBSD/mips cpu support.
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*/
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/*
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* Macros to find the CPU architecture we're on at run-time,
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* or if possible, at compile-time.
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*/
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#if (MIPS1 + MIPS3) == 1
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#ifdef MIPS1
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# define CPUISMIPS3 0
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#endif /* mips1 */
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#ifdef MIPS3
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# define CPUISMIPS3 1
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#endif /* mips1 */
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#else /* run-time test */
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extern int cpu_arch;
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#define CPUISMIPS3 (cpu_arch == 3)
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#endif /* run-time test */
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/*
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* definitions of cpu-dependent requirements
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* referenced in generic code
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*/
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#define cpu_wait(p) /* nothing */
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#define cpu_swapout(p) panic("cpu_swapout: can't get here");
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/*
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* Arguments to hardclock and gatherstats encapsulate the previous
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* machine state in an opaque clockframe.
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*/
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struct clockframe {
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int pc; /* program counter at time of interrupt */
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int sr; /* status register at time of interrupt */
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};
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/*
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* A port must provde CLKF_USERMODE() and CLKF_BASEPRI() for use
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* in machine-independent code. These differ on r4000 and r3000 systems;
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* provide them in the port-dependent file that includes this one, using
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* the macros below.
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*/
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/* mips1 versions */
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#define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV)
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#define MIPS1_CLKF_BASEPRI(framep) \
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((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_ENA_PREV)) == 0)
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/* mips3 versions */
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#define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER)
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#define MIPS3_CLKF_BASEPRI(framep) \
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((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_ENAB)) == 0)
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#define CLKF_PC(framep) ((framep)->pc)
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#define CLKF_INTR(framep) (0)
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#if defined(MIPS3) && !defined(MIPS1)
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#define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep)
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#define CLKF_BASEPRI(framep) MIPS3_CLKF_BASEPRI(framep)
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#endif
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#if !defined(MIPS3) && defined(MIPS1)
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#define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep)
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#define CLKF_BASEPRI(framep) MIPS1_CLKF_BASEPRI(framep)
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#endif
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#if defined(MIPS3) && defined(MIPS1)
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#define CLKF_USERMODE(framep) \
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((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep))
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#define CLKF_BASEPRI(framep) \
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((CPUISMIPS3) ? MIPS3_CLKF_BASEPRI(framep): MIPS1_CLKF_BASEPRI(framep))
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#endif
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/*
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* Preempt the current process if in interrupt from user mode,
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* or after the current trap/syscall if in system mode.
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*/
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#define need_resched() { want_resched = 1; aston(); }
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/*
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* Give a profiling tick to the current process when the user profiling
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* buffer pages are invalid. On the MIPS, request an ast to send us
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* through trap, marking the proc as needing a profiling tick.
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*/
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#define need_proftick(p) { (p)->p_flag |= P_OWEUPC; aston(); }
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/*
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* Notify the current process (p) that it has a signal pending,
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* process as soon as possible.
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*/
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#define signotify(p) aston()
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#define aston() (astpending = 1)
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int astpending; /* need to trap before returning to user mode */
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int want_resched; /* resched() was called */
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/*
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* CTL_MACHDEP definitions.
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*/
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#define CPU_CONSDEV 1 /* dev_t: console terminal device */
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#define CPU_MAXID 2 /* number of valid machdep ids */
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#define CTL_MACHDEP_NAMES { \
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{ 0, 0 }, \
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{ "console_device", CTLTYPE_STRUCT }, \
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}
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/*
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* MIPS CPU types (cp_imp).
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*/
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#define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */
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#define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */
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#define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */
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#define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */
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#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */
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#define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */
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#define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */
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#define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */
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#define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */
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#define MIPS_UNKC1 0x0b /* unnanounced product cpu ISA III */
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#define MIPS_UNKC2 0x0c /* unnanounced product cpu ISA III */
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#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
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#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
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#define MIPS_R3SONY 0x21 /* Sony R3000 based CPU ISA I */
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#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */
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#define MIPS_R3NKK 0x23 /* NKK R3000 based CPU ISA I */
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/*
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* MIPS FPU types
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*/
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#define MIPS_SOFT 0x00 /* Software emulation ISA I */
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#define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */
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#define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */
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#define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */
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#define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */
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#define MIPS_R4010 0x05 /* MIPS R4000/R4400 FPC ISA II */
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#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */
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#define MIPS_R10010 0x09 /* MIPS R10000/T5 FPU ISA IV */
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#define MIPS_R4210 0x0a /* MIPS R4200 FPC (ICE) ISA III */
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#define MIPS_UNKF1 0x0b /* unnanounced product cpu ISA III */
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#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
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#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
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#define MIPS_R3SONY 0x21 /* Sony R3000 based FPU ISA I */
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#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */
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#define MIPS_R3NKK 0x23 /* NKK R3000 based FPU ISA I */
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/*
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* Enable realtime clock (always enabled).
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*/
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#define enablertclock()
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#endif /* _CPU_H_ */
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